Set UART0 to "PchSerialIoSkipInit" so the pins for this device are not
set back to native mode by FSP when configured as GPIO input by coreboot.
Now that FSP is not touching the pins I also removed the workaround to
reconfigure the pins after FSP.
BUG=b:35647877
BRANCH=none
TEST=Verify that GPP_C8-GPP_C11 are configured as GPIO input once the OS
is booted and they are not set back to native function by FSP.
Change-Id: I688433e8b6556c5f3e2c374481cd29d8351c0032
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e49b866c7c
Original-Change-Id: Ifec4fa3e66ceeb660bad00c66bc7bd44bb457a01
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19264
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480102
These lines act as inputs to both EC and AP and when the corresponding
TCPC mux is in low power mode the line is floating. Add an internal
pull-down to each GPIO to prevent it from floating in this state.
BUG=b:35775012
BRANCH=none
TEST=Verify that the kernel does not see a device present on DP when
the TCPC mux is in low power mode.
Change-Id: I6d940004364e4a5cc338ff2063d034d12c1dcf88
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 30783d84cf
Original-Change-Id: Ie229f84871e9994467c0ab660cc7e271a51d9cbb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19263
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480101
With EuP and PME enabled the USB power turns off during S5.
BUG=none
BRANCH=none
TEST=none
Change-Id: I57d70a85586832384e5c6fc9d65a681404b7a48a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5ad939679f
Original-Change-Id: I8b9fd7bb308f544401f90f8aa5ffaec61251b2b3
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/19073
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/480100
In order to support a standard "docked" config disable Deep S3 when
connected to AC power. This allows USB devices to wake the device
from suspend if it is externally powered, but still retains the
lower power state when running on battery.
BUG=b:36723679
BRANCH=none
TEST=manual testing on Eve for USB wake behavior:
1) when suspended on battery USB keyboard does not wake
2) when suspended while connected to AC a USB keyboard does wake
3) if suspended with AC, and then AC is removed, system does not
wake with USB keyboard
4) if suspended without AC, and then AC is added, system does not
wake with USB keyboard (it cannot get enabled without waking and
re-suspending)
Change-Id: I522b50c16fa0c4c3ba3731075fe29d3e799935d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 73ff0fbd2e
Original-Change-Id: I670e39d42cdb5b80612206da899be82ef3b2cbf2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19240
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/480098
Enable the Intel WiFi SAR feature for Eve, which will be used to
provide wifi power tables based on values read from VPD.
This is enabled based on CONFIG_CHROMEOS because it relies on the
presence of VPD code from vendorcode/google/chromeos.
BUG=b:36727652
BRANCH=none
TEST=test on Eve by setting "wifi_sar" in VPD and ensuring that
the ACPI WIFI device gets the expected "WRDS" and "EWRD" tables
with the values that were set in VPD.
Change-Id: I124395715f3b074c74ce8b9436b561143aceac46
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 654c8de9f1
Original-Change-Id: I11c129baca891221177575108ac09ba1707b516e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19241
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480097
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled
in both DC and AC states. However since using Deep S3 disables some
expected features like wake-on-USB it is not always desired to enable the
same state in both modes.
To address this split the setting and add a separate config for Deep Sx in
AC and DC states.
All motherboards that set this config were updated, but there is no actual
change in behavior in this commit.
BUG=b:36723679
BRANCH=none
TEST=This commit has no runtime visible changes, I verified on Eve that the
Deep SX config registers are unchanged, and it compiles for all affected boards.
Change-Id: Ifceb6039323c6a755ea4a0c26356aa778e2d04d1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1fe32d6bb2
Original-Change-Id: I590f145847785b5a7687f235304e988888fcea8a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19239
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480096
These lines act as inputs to both EC and AP. Thus, add internal
pull-downs to prevent them from floating.
BUG=b:35648530
Change-Id: Ia73ecfe432c5543d37d5ff166124d364006138ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bcbba801b8
Original-Change-Id: I42326c810775d5449e99e52e81870970247ce335
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19243
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/480095
Put all configs required for enabling cr50 SPI TPM on poppy under
POPPY_USE_SPI_TPM so that it can be enabled any time for testing SPI
TPM on this board.
Also, add required callback for irq status and devicetree config for
GSPI0.
BUG=b:36873582
Change-Id: Ie467753b802ccce1d50c5a982da77872ac274f30
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 82010835bf
Original-Change-Id: I67793093c006c1325fc16f669a96126525f83243
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19238
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/480094
1. Move common TIS macros to include/tpm.h.
2. Use common TIS macros while referring to status and access registers.
3. Add a new function claim_locality to properly check for required
access bits and claim locality 0.
BUG=b:36873582
Change-Id: I64501d5d78b82744e85433f34d0f94f82b45b370
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 260b297a89
Original-Change-Id: I11bf3e8b6e1f50b7868c9fe4394a858488367287
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19213
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/480093
CBGFX currently doesn't support portrait screens at all. This will have
to be fixed eventually but might take a bit of effort. As a first step
to make devices with a portrait panel somewhat usable, this patch will
just force a square canvas on these panels and keep the bottom part of
the screen black.
Also switch set_pixel to calculate framebuffer position via
bytes_per_line instead of x_resolution. This is supposed to be the
canonical way to do that and may differ in cases where the display
controller requires a certain alignment from framebuffer lines.
BRANCH=none
BUG=b:35774871
TEST=Boot Rowan in developer mode and see output on the
panel; below the developer screen square is completely black
Change-Id: I5e5423e5fe166b1fea54ab16f7e0dd31fcce00d7
Original-Change-Id: I47dd3bf95ab8a7d8b7e1913e0ddab346eedd46f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/479613
Commit-Ready: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
With recent change to use common block PCR (ccd8700c),
IOSF_BASE_ADDRESS was renamed to PCR_BASE_ADDRESS. However, SD card
change (99ce8a9b) was not rebased on top of it, so IOSF_BASE_ADDRESS
slipped into the tree. Fix this by replacing all occurrences of
IOSF_BASE_ADDRESS by PCR_BASE_ADDRESS.
CQ-DEPEND=CL:477153
BUG=None
BRANCH=reef
TEST=Compiles successfully for reef.
Change-Id: I40eb07be306035c940fc960896e0807d6c73bafa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19277
Tested-by: build bot (Jenkins)
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/477410
Reviewed-by: Martin Roth <martinroth@chromium.org>
Currently sdcard CD host ownership is always owned by the GPIO driver.
Due to this sdcard detection fails during initial boot process and OS
fails to boot from sdcard.
This implements change in host ownership from acpi to GPIO driver when
kernel starts booting.
CQ-DEPEND=CL:477410
BUG=b:35648535
BRANCH=reef
TEST=Check OS boot from sdcard.
Change-Id: I042a8762dc1f9cb73e6a24c1e7169c9746b2ee14
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18947
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/477153
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
The original document was written and committed with no regard to line
lengths. This makes it easier to write. Now it needs to be easier to
read, so wrap the lines at 80 characters where possible.
- A couple of headings had to be rewritten to keep them under 80
characters. This required the addition of a new paragraph that had
the old header.
- Remove URL text that was just duplicating the URL.
- All other text is the same, just wrapped.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6c450c36dea4ae5eb6bbaf7fdb46d6b57d475137
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ccfea16cd4
Original-Change-Id: I44833c28750714fccb87296868c1ff78ab7f1d07
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19076
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/475712
Using i2c_block_read speeds up reading SPD four to fivefold compared
to sequential byte read.
TESTED on Intel D945GCLF.
BUG=none
BRANCH=none
TEST=none
Change-Id: I28829a1ad5b834a9b32ba13815bdd55f78d96d13
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2a7c519c89
Original-Change-Id: I6d768a2ba128329168f26445a4fca6921c0c8642
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18927
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/475711
Scarlet don't have eDP and MIPI driver is not ready, skipping
display for now or else Scarlet would be stuck in
reading eDP HPD because there even not power for it.
TEST=boot to kernel on Scarlet
Change-Id: Id2558eeb60900a25f2c99c42b338db2d9d80fd57
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4f4410dcbc
Original-Change-Id: I02ab4ef21bf77b98414f537aca57b46c11922348
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19237
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/474137
Due to issues with stability limit the SKU with K4EBE304EB-EGCF
memory to 1600MHz instead of 1866MHz.
BUG=b:37172778
BRANCH=none
TEST=pass stress testing on devices with this memory
Change-Id: I3dd16517ce8043d9a71e2da553f81861504a29ea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 08117c412c
Original-Change-Id: I02af7e9c35e2c5b0b85223d58025cbd29841d973
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19227
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/474136
This is needed if one wants to use the header more than once.
BUG=none
BRANCH=none
TEST=none
Change-Id: If43ac3dafbb8e6b9052d6af9206d586d5a466ce1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f170e71630
Original-Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19029
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/474135
Create Intel Common RTC code. This code currently only
contains the code for configuring RTC required in Bootblock phase
which has the following programming -
* Enable upper 128 bytes of CMOS.
BUG=none
BRANCH=none
TEST=none
Change-Id: I25d743418a00626e5fb199ce26c095acbf01902d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e84723e02
Original-Change-Id: Id9dfcdbc300c25f43936d1efb5d6f9d81d3c8453
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18558
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/474131
IOSF_SB message space is used to access registers mapped
on IOSF-SB. These registers include uncore CRs (configuration
registers) and chipset specific registers. The Private
Configuration Register (PCR) space is accessed on IOSF-SB
using destination ID also known as Port ID.
Access to IOSF-SB by the Host or System Agent is possible
over PSF via the Primary to Sideband Bridge (P2SB). P2SB will
forward properly formatted register access requests as CRRd and
CRWr request via IOSF-SB.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id92e85334956d993168005f7737b623da039cbbb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d579199f96
Original-Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18669
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/474128
Update the I2C rise/fall timings based on newly measured values
on a new board with updated pull-up resistor values.
Touchscreen: rise time 98ns, fall time 38ms
Touchpad: rise time 111ns, fall time 41ns
TPM: rise time 112ns, fall time 34ns
BUG=b:35583133
BRANCH=none
TEST=Each I2C bus frequency was verified on a scope to be ~400MHz
Change-Id: Ib2b0598fb10c3e0e21161583362fc317d3e1f5c9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 92dde2fdd7
Original-Change-Id: Ibb3a15fa0cc862f36c1b9c63ac7847221020c4c0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19202
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/474127
There is only one user for spi_get_config i.e. SPI ACPI. Also, the
values provided by spi_get_config are constant for now. Thus, get rid
of the spi_get_config call and fill in these constant values in SPI
ACPI code itself. If there is a need in the future to change these,
appropriate device-tree configs can be added.
BUG=b:36873582
Change-Id: Id2a1447d3112dc0f33f35b1357a039f1852da44d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5bda642bcb
Original-Change-Id: Ied38e2670784ee3317bb12e542666c224bd9e819
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19203
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/472721
When a platform is using postcar stage it's by definition not
tearing down cache-as-ram from within romstage prior to loading
ramstage. Because of this property there's no need to migrate
CAR_GLOBAL variables to cbmem.
BUG=none
BRANCH=none
TEST=none
Change-Id: I34c0ae5c9f5e862ad523c58ceeeb1ab3873bc4c3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc17cdef0d
Original-Change-Id: I7c683e1937c3397cbbba15f0f5d4be9e624ac27f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19215
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/472720
Bottom five LSBs are used to store the running frequency
of memory clock.
BUG=none
BRANCH=none
TEST=none
Change-Id: If241c224ecb5b5aed3e308d126cd1d7d0314417e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e522258907
Original-Change-Id: I2dfcf1950883836499ea2ca95f9eb72ccdfb979c
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19042
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/472718
The EC may take very long for the first command on a cold boot (~180ms
witnessed). Since this needs an incredibly long timeout, we do this
single command manually.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9671c6a3ad5127e41808247be13c99dae315ab5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e223c3aee9
Original-Change-Id: I3302622a845ac6651bc7f563370d8f0511836f94
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/18707
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/472717
Enable SS link trunk clock gating & D3hot when device enters
D3 state.
Similarly disable SS link trunk clock gating & D3hot when device enters
D0 state
TEST=Build & boot Poppy board. Check working for XHCI wake when DUT
is in S3.
Change-Id: I1fee9776173a5e15436da3839868584187cddc51
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fb7937918a
Original-Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18879
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/472714
This patch cleans up the code by:
o adding necessary default definitions to Kconfig
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
devicetree.cb and minnow3.fmd carried over a lot of code from google/reef
which is not correct for Minnow3 hardware. Minnow3 is not intended to
boot Chrome OS and does not need Chrome related flash regions. The
erroneous code is removed.
These changes are the same as those done for leafhill in commit:
6a48923 mainboard/intel/leafhill: Clean up
This was tested by building with the new configuration and
booting to UEFI Payload
BUG=none
BRANCH=none
TEST=none
Change-Id: I55cba41ba898e8e4f2b74805ae9cf5a391adc277
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 44ff10eaa6
Original-Change-Id: I620dcbcd622f9326917c74b2a38984d9e49cff2b
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18963
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/472713
This fixes the following issues, with no functional changes:
ERROR:POINTER_LOCATION: "foo * bar" should be "foo *bar"
ERROR:SPACING: space required after that ',' (ctx:VxV)
WARNING:LONG_LINE_COMMENT: line over 80 characters
WARNING:SPACE_BEFORE_TAB: please, no space before tabs
ERROR:FUNCTION_WITHOUT_ARGS: Bad function definition
ERROR:SPACING: space prohibited before that close parenthesis ')'
WARNING:RETURN_VOID: void function return statements are not generally
useful
2 unfixed issues:
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
Verified that the binary was the same before and after the changes.
BUG=none
BRANCH=none
TEST=none
Change-Id: If7a8efa7bd02cb70eba10686396274d44953d6e9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9931f66581
Original-Change-Id: Ie9afb50e268f4140872e39fe8bede231a43d5cc6
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19078
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/472712
All boards select INTEL_EDID, move it to nb folder.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie41e0d5dc6a50e9b2ba170cf1ad6c25b74a47f2e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 46cf5c29b3
Original-Change-Id: I35f075a87f2d841856b208f9440cf41af6a3c8e6
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19086
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/472711
This adds a gru libpayload config, that should fit all gru-based
devices such as kevin.
As gru-based devices are CrOS devices, select the associated config
to enable CrOS-specific features.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4e7112bb82e790719bc608ce8fe2f852f56e3ce2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 038818f00c
Original-Change-Id: I6e79b763fc497c126612b8786a669a33b57ea29f
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/19137
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/472710
Move odt stretch into own function.
Apply workaround on SandyBridge C-stepping CPU only.
Apply odt stretch on all other CPU types.
Don't depend on empty DIMM detection, as in case one slot
is empty ref_card_offset is zero.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie348a49ed33b841503f0e54b24969f7faf02b546
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 19c3dad0ad
Original-Change-Id: I4320f14e0522ec997b1f9f3b12ba2c2070ee8e9e
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17616
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/472709
quick_ram_check doesn't change contents of memory.
Run it in S3 resume, too.
BUG=none
BRANCH=none
TEST=none
Change-Id: I903fd25adfa117b0b466a7c191ae2bf54d7af867
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 77db3e153b
Original-Change-Id: Icaf3650fadbb3bb87d8c780a9e79737c3cf7eb06
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17615
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/472708
Silency noisy raminit logging by:
* Removing verbose logging from loops.
* Printing detailed summary at end of loop instead.
* Using the same scheme already present in some functions.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1f947fcece53776fa71c55a5557c57ef526c91a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 368b615243
Original-Change-Id: I412d81592436ac0d2422caf396c64e0c34acc2d1
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17611
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/472707
Remove cross rank/cross channel dependency.
I guess this is a mistake that could lead to instabilities.
Tested on Lenovo T430 (Intel IvyBridge).
BUG=none
BRANCH=none
TEST=none
Change-Id: I9983d6c92b2729c602f4de1a593bd250e1fc80e4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c8cb97ea7
Original-Change-Id: I899db907cd2d2197fd81eda4c4656fb1e570c18f
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17610
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/472706
Linking should allow to link depending on possible future variants.
E.g. in Makefile.inc romstage-$(CONFIG_'VARIANT0') += gpio_variant0.c
etc.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifba4887fe5c212000bedd540e5f8ebf1f73c88e2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7dee97454a
Original-Change-Id: I88b5ef8e12ac606751952a493f626e1b146e98f7
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19139
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/471526
