coreboot for the Switch
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Duncan Laurie 6377341e7e UPSTREAM: mainboard/google/eve: Set UART0 to skip initialization in FSP
Set UART0 to "PchSerialIoSkipInit" so the pins for this device are not
set back to native mode by FSP when configured as GPIO input by coreboot.

Now that FSP is not touching the pins I also removed the workaround to
reconfigure the pins after FSP.

BUG=b:35647877
BRANCH=none
TEST=Verify that GPP_C8-GPP_C11 are configured as GPIO input once the OS
is booted and they are not set back to native function by FSP.

Change-Id: I688433e8b6556c5f3e2c374481cd29d8351c0032
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e49b866c7c
Original-Change-Id: Ifec4fa3e66ceeb660bad00c66bc7bd44bb457a01
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19264
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480102
2017-04-18 13:18:55 -07:00
configs UPSTREAM: configs/builder: Remove pre-defined VGA bios file 2017-01-22 05:03:18 -08:00
Documentation UPSTREAM: Documentation: Reflow Kconfig.md 2017-04-12 11:35:27 -07:00
payloads UPSTREAM: libpayload: cbgfx: Show square images on portrait displays 2017-04-17 22:50:24 -07:00
src UPSTREAM: mainboard/google/eve: Set UART0 to skip initialization in FSP 2017-04-18 13:18:55 -07:00
util UPSTREAM: util/intelmetool: Check for NULL return from pci_lookup_name 2017-04-07 07:03:31 -07:00
.checkpatch.conf Drop --exclude statement from .checkpatch.conf 2017-03-13 17:53:59 -07:00
.clang-format Provide coreboot coding style formalisation file for clang-format 2015-11-10 00:49:03 +01:00
.gitignore UPSTREAM: .gitignore: ignore *.swo and option *.roms 2017-03-10 10:54:46 -08:00
.gitmodules Make upstream tree CrOS SDK friendly 2016-05-12 15:42:17 -06:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COMMIT-QUEUE.ini DO NOT UPSTREAM: COMMIT-QUEUE: Configure pre-CQ for more coverage 2017-03-29 13:43:13 -07:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
gnat.adc UPSTREAM: gnat.adc: Do not generate assertion code for Refined_Post 2016-11-03 14:44:05 -07:00
MAINTAINERS UPSTREAM: MAINTAINERS: Update list 2017-03-08 05:13:03 -08:00
Makefile UPSTREAM: Remove libverstage as separate library and source file class 2017-03-29 13:43:09 -07:00
Makefile.inc UPSTREAM: Makefile.inc: Fix jenkins build of nvramcui & coreinfo 2017-04-03 11:48:55 -07:00
PRESUBMIT.cfg Make upstream tree CrOS SDK friendly 2016-05-12 15:42:17 -06:00
README UPSTREAM: Remove extra newlines from the end of all coreboot files. 2016-08-04 23:36:56 -07:00
toolchain.inc UPSTREAM: Remove libverstage as separate library and source file class 2017-03-29 13:43:09 -07:00

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.