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UPSTREAM: soc/intel/skylake: Use RTC common code

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This patch uses common RTC library to enable
upper 128 byte bank of RTC RAM.

BUG=none
BRANCH=none
TEST=none

Change-Id: I4d6a7c5d4bf02f429f640eb499af0e698ae704a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e0268d3e1a
Original-Change-Id: Ibcbaf5061e96a67815116a9f7a03be515997be6d
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18701
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/474132
This commit is contained in:
Subrata Banik 2017-03-09 13:56:17 +05:30 • committed by chrome-bot
parent e3f9bdb2d3
commit 5804104ea5
2 changed files with 3 additions and 10 deletions
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1
src/soc/intel/skylake/Kconfig
View file

@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_GSPI
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_LPSS_I2C

12
src/soc/intel/skylake/bootblock/pch.c
View file

@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/itss.h>
@ -45,9 +46,6 @@
#define PCR_DMI_LPCIOD 0x2770
#define PCR_DMI_LPCIOE 0x2774
#define PCR_RTC_CONF 0x3400
#define PCR_RTC_CONF_UCMOS_EN 0x4
/*
* Enable Prefetching and Caching.
*/
@ -247,12 +245,6 @@ static void soc_config_tco(void)
outw(tcocnt, tcobase + TCO1_CNT);
}
static void soc_config_rtc(void)
{
/* Enable upper 128 bytes of CMOS */
pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN);
}
static void enable_heci(void)
{
device_t dev = PCH_DEV_CSE;
@ -322,7 +314,7 @@ void pch_early_init(void)
/* Set up GPE configuration */
pmc_gpe_init();
soc_config_rtc();
enable_rtc_upper_bank();
enable_heci();
}