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UPSTREAM: nb/intel/sandybridge/raminit: Fix odt stretch
Move odt stretch into own function.
Apply workaround on SandyBridge C-stepping CPU only.
Apply odt stretch on all other CPU types.
Don't depend on empty DIMM detection, as in case one slot
is empty ref_card_offset is zero.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie348a49ed33b841503f0e54b24969f7faf02b546
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 19c3dad0ad
Original-Change-Id: I4320f14e0522ec997b1f9f3b12ba2c2070ee8e9e
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/17616
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/472709
This commit is contained in:
parent
25dc0a113b
commit
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1 changed files with 35 additions and 54 deletions
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@ -189,10 +189,39 @@ void dram_xover(ramctr_timing * ctrl)
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}
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}
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void dram_timing_regs(ramctr_timing * ctrl)
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static void dram_odt_stretch(ramctr_timing *ctrl, int channel)
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{
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u32 reg, addr, val32, cpu, stretch;
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struct cpuid_result cpures;
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u32 reg, addr, cpu, stretch;
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stretch = ctrl->ref_card_offset[channel];
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/* ODT stretch: Delay ODT signal by stretch value.
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* Useful for multi DIMM setups on the same channel. */
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cpures = cpuid(1);
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cpu = cpures.eax;
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if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) {
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if (stretch == 2)
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stretch = 3;
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addr = 0x400 * channel + 0x401c;
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reg = MCHBAR32(addr) & 0xffffc3ff;
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reg |= (stretch << 12);
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reg |= (stretch << 10);
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MCHBAR32(addr) = reg;
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printram("OTHP Workaround [%x] = %x\n", addr, reg);
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} else {
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// OTHP
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addr = 0x400 * channel + 0x400c;
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reg = MCHBAR32(addr) & 0xfff0ffff;
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reg |= (stretch << 16);
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reg |= (stretch << 18);
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MCHBAR32(addr) = reg;
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printram("OTHP [%x] = %x\n", addr, reg);
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}
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}
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void dram_timing_regs(ramctr_timing *ctrl)
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{
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u32 reg, addr, val32;
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int channel;
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FOR_ALL_CHANNELS {
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@ -232,52 +261,7 @@ void dram_timing_regs(ramctr_timing * ctrl)
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MCHBAR32(addr) |= 0x00020000;
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// ODT stretch
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reg = 0;
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cpures = cpuid(1);
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cpu = cpures.eax;
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if (IS_IVY_CPU(cpu)
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|| (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_D2(cpu))) {
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stretch = 2;
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addr = 0x400 * channel + 0x400c;
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printram("ODT stretch [%x] = %x\n",
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0x400 * channel + 0x400c, reg);
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reg = MCHBAR32(addr);
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if (((ctrl->rankmap[channel] & 3) == 0)
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|| (ctrl->rankmap[channel] & 0xc) == 0) {
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// Rank 0 - operate on rank 2
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reg = (reg & ~0xc0000) | (stretch << 18);
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// Rank 2 - operate on rank 0
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reg = (reg & ~0x30000) | (stretch << 16);
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printram("ODT stretch [%x] = %x\n", addr, reg);
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MCHBAR32(addr) = reg;
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}
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} else if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) {
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stretch = 3;
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addr = 0x400 * channel + 0x401c;
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reg = MCHBAR32(addr);
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if (((ctrl->rankmap[channel] & 3) == 0)
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|| (ctrl->rankmap[channel] & 0xc) == 0) {
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// Rank 0 - operate on rank 2
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reg = (reg & ~0x3000) | (stretch << 12);
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// Rank 2 - operate on rank 0
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reg = (reg & ~0xc00) | (stretch << 10);
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printram("ODT stretch [%x] = %x\n", addr, reg);
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MCHBAR32(addr) = reg;
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}
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} else {
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stretch = 0;
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}
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dram_odt_stretch(ctrl, channel);
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// REFI
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reg = 0;
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@ -3155,7 +3139,7 @@ void prepare_training(ramctr_timing * ctrl)
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void set_4008c(ramctr_timing * ctrl)
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{
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int channel, slotrank;
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u32 reg;
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FOR_ALL_POPULATED_CHANNELS {
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u32 b20, b4_8_12;
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int min_320c = 10000;
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@ -3176,11 +3160,8 @@ void set_4008c(ramctr_timing * ctrl)
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else
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b4_8_12 = 0x2220;
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reg = read32(DEFAULT_MCHBAR + 0x400c + (channel << 10));
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write32(DEFAULT_MCHBAR + 0x400c + (channel << 10),
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(reg & 0xFFF0FFFF)
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| (ctrl->ref_card_offset[channel] << 16)
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| (ctrl->ref_card_offset[channel] << 18));
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dram_odt_stretch(ctrl, channel);
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write32(DEFAULT_MCHBAR + 0x4008 + (channel << 10),
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0x0a000000
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| (b20 << 20)
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