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UPSTREAM: mainboard/google/eve: Set UART0 to skip initialization in FSP

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Set UART0 to "PchSerialIoSkipInit" so the pins for this device are not
set back to native mode by FSP when configured as GPIO input by coreboot.

Now that FSP is not touching the pins I also removed the workaround to
reconfigure the pins after FSP.

BUG=b:35647877
BRANCH=none
TEST=Verify that GPP_C8-GPP_C11 are configured as GPIO input once the OS
is booted and they are not set back to native function by FSP.

Change-Id: I688433e8b6556c5f3e2c374481cd29d8351c0032
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e49b866c7c
Original-Change-Id: Ifec4fa3e66ceeb660bad00c66bc7bd44bb457a01
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19264
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/480102
This commit is contained in:
Duncan Laurie 2017-04-13 01:40:53 -07:00 • committed by chrome-bot
parent fcb29d317a
commit 6377341e7e
3 changed files with 1 additions and 12 deletions
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2
src/mainboard/google/eve/devicetree.cb
View file

@ -204,7 +204,7 @@ chip soc/intel/skylake
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSpi0] = PchSerialIoPci,
[PchSerialIoIndexSpi1] = PchSerialIoPci,
[PchSerialIoIndexUart0] = PchSerialIoPci,
[PchSerialIoIndexUart0] = PchSerialIoSkipInit,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"

7
src/mainboard/google/eve/gpio.h
View file

@ -231,13 +231,6 @@ static const struct pad_config early_gpio_table[] = {
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
};
static const struct pad_config late_gpio_table[] = {
/* UART0_RXD */ PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */
/* UART0_TXD */ PAD_CFG_GPI(GPP_C9, NONE, DEEP), /* FP_RST_ODL */
/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* PCH_FPS_MCU_NRST_ODL */
/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* PCH_FPS_MCU_BOOT0 */
};
#endif
#endif

4
src/mainboard/google/eve/mainboard.c
View file

@ -19,10 +19,7 @@
#include <device/device.h>
#include <ec/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <soc/nhlt.h>
#include "gpio.h"
static const char *oem_id_maxim = "GOOGLE";
static const char *oem_table_id_maxim = "EVEMAX";
@ -30,7 +27,6 @@ static const char *oem_table_id_maxim = "EVEMAX";
static void mainboard_init(device_t dev)
{
mainboard_ec_init();
gpio_configure_pads(late_gpio_table, ARRAY_SIZE(late_gpio_table));
}
static unsigned long mainboard_write_acpi_tables(