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UPSTREAM: soc/intel/common/block: Add Intel common RTC code support

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Create Intel Common RTC code. This code currently only
contains the code for configuring RTC required in Bootblock phase
which has the following programming -
* Enable upper 128 bytes of CMOS.

BUG=none
BRANCH=none
TEST=none

Change-Id: I25d743418a00626e5fb199ce26c095acbf01902d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e84723e02
Original-Change-Id: Id9dfcdbc300c25f43936d1efb5d6f9d81d3c8453
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18558
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/474131
This commit is contained in:
Barnali Sarkar 2017-02-17 18:15:22 +05:30 • committed by chrome-bot
parent 822617b75a
commit e3f9bdb2d3
4 changed files with 57 additions and 0 deletions
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21
src/soc/intel/common/block/include/intelblocks/rtc.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOC_INTEL_COMMON_BLOCK_RTC_H
#define SOC_INTEL_COMMON_BLOCK_RTC_H
void enable_rtc_upper_bank(void);
#endif /* SOC_INTEL_COMMON_BLOCK_RTC_H */

4
src/soc/intel/common/block/rtc/Kconfig Normal file
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config SOC_INTEL_COMMON_BLOCK_RTC
bool
help
Intel Processor common RTC support

1
src/soc/intel/common/block/rtc/Makefile.inc Normal file
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bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_RTC) += rtc.c

31
src/soc/intel/common/block/rtc/rtc.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/pcr_ids.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
/* RTC PCR configuration */
#define PCR_RTC_CONF 0x3400
#define PCR_RTC_CONF_UCMOS_EN (1 << 2)
#define PCR_RTC_CONF_LCMOS_LOCK (1 << 3)
#define PCR_RTC_CONF_UCMOS_LOCK (1 << 4)
#define PCR_RTC_CONF_RESERVED (1 << 31)
void enable_rtc_upper_bank(void)
{
/* Enable upper 128 bytes of CMOS */
pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN);
}