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UPSTREAM: soc/intel/apollolake: Use RTC common code

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This patch uses common RTC library to enable
upper 128 byte bank of RTC RAM.

BUG=none
BRANCH=none
TEST=none

Change-Id: I578715948bbf18f770e2bdd24b12d3554b5db6f9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8bf69d3078
Original-Change-Id: I55e196f6c5282d7c0a31b3980da8ae71764df611
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18700
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/474133
This commit is contained in:
Subrata Banik 2017-03-09 13:43:54 +05:30 • committed by chrome-bot
parent 5804104ea5
commit d040636478
2 changed files with 3 additions and 10 deletions
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1
src/soc/intel/apollolake/Kconfig
View file

@ -55,6 +55,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_SMI
select SOC_INTEL_COMMON_SPI_FLASH_PROTECT

12
src/soc/intel/apollolake/bootblock/bootblock.c
View file

@ -20,6 +20,7 @@
#include <device/pci.h>
#include <intelblocks/pcr.h>
#include <intelblocks/systemagent.h>
#include <intelblocks/rtc.h>
#include <lib.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
@ -28,15 +29,11 @@
#include <soc/mmap_boot.h>
#include <soc/systemagent.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h>
#include <soc/uart.h>
#include <spi-generic.h>
#include <timestamp.h>
#define PCR_RTC_CONF 0x3400
#define PCR_RTC_CONF_UCMOS_EN 0x4
static const struct pad_config tpm_spi_configs[] = {
PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
};
@ -47,11 +44,6 @@ static void tpm_enable(void)
gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
}
static void enable_cmos_upper_bank(void)
{
pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN);
}
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
device_t dev;
@ -71,7 +63,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MASTER);
enable_cmos_upper_bank();
enable_rtc_upper_bank();
/* Call lib/bootblock.c main */
bootblock_main_with_timestamp(base_timestamp);