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UPSTREAM: soc/intel/common/block: Add Intel common UART code

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Create Intel Common UART driver code. This code does
below UART configuration for bootblock phase.

* Program BAR
* Configure reset register
* Configure clock register

BUG=none
BRANCH=none
TEST=none

Change-Id: Iba752e0a751c1eb37f68a401d237de21d0327dcd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 01d75f4172
Original-Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18952
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/475715
This commit is contained in:
Aamir Bohra 2017-03-30 20:12:21 +05:30 • committed by chrome-bot
parent 42bbbaca04
commit 8a3cb560f4
4 changed files with 65 additions and 0 deletions
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24
src/soc/intel/common/block/include/intelblocks/uart.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOC_INTEL_COMMON_BLOCK_UART_H
#define SOC_INTEL_COMMON_BLOCK_UART_H
#include <arch/io.h>
void uart_common_init(device_t dev, uintptr_t baseaddr,
uint32_t clk_m_val, uint32_t clk_n_val);
#endif /* SOC_INTEL_COMMON_BLOCK_UART_H */

5
src/soc/intel/common/block/uart/Kconfig Normal file
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config SOC_INTEL_COMMON_BLOCK_UART
bool
select SOC_INTEL_COMMON_BLOCK_LPSS
help
Intel Processor common UART support

1
src/soc/intel/common/block/uart/Makefile.inc Normal file
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bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c

35
src/soc/intel/common/block/uart/uart.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci_def.h>
#include <intelblocks/lpss.h>
#include <intelblocks/uart.h>
void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val,
uint32_t clk_n_val)
{
/* Set UART base address */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr);
/* Enable memory access and bus master */
pci_write_config32(dev, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Take UART out of reset */
lpss_reset_release(baseaddr);
/* Set M and N divisor inputs and enable clock */
lpss_clk_update(baseaddr, clk_m_val, clk_n_val);
}