Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1060 f3766cd6-281f-0410-b1cd-43a5c92072e9
by Stefan.
The only changes left from r1057 are:
- Added comments
- Two initial pushes of 0x00000000 (32 bits each) to the stack as safety
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1058 f3766cd6-281f-0410-b1cd-43a5c92072e9
with a wrong calling convention of stage1_phase1() this caused stage1 to
assume BIST had failed.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1057 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1053 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1052 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1051 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1050 f3766cd6-281f-0410-b1cd-43a5c92072e9
Make statics non-static (we don't do buildrom any more)
Index: northbridge/intel/i945/raminit.c
remove snarf-o that left k8 in (I used wrong script I guess?)
Index: southbridge/intel/i82801gx/libsmbus.c
Corrections (minor)
Index: southbridge/intel/i82801gx/stage1_smbus.c
static to global
Index: mainboard/kontron/986lcd-m/stage1_debug.c
don't include statictree.c
Index: mainboard/kontron/986lcd-m/stage1.c
Remove functions that have to be in initram.
Index: mainboard/kontron/986lcd-m/initram.c
Add functions. This is all about splitting auto.c into stage1 and initram.
stage1 is very small and limited.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1049 f3766cd6-281f-0410-b1cd-43a5c92072e9
pci_set_resources. There is no matching pci_bus_set_resources, so it's
confusing to see the dev function in the bus structures.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
As DBE61 support now runs ram_check for non-debug purposes and has expected failures
on DBE61A, downgrade the per-address looped fail notification printk and other messages
from BIOS_ERR to BIOS_DEBUG.
Document that if something is wanted to be reported in non-debug loglevels, one should
do so in the caller based on the return value.
Tweak a debug string in ram_verify to be more descriptive.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1047 f3766cd6-281f-0410-b1cd-43a5c92072e9
that it uses the correct functions. Using the device functions on the bridge
was not so good for it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1046 f3766cd6-281f-0410-b1cd-43a5c92072e9
device/pci_device.c:
Only update IDs if:
- The device is on the mainboard
- The device has a Vendor ID and Device ID
- The device has a set_subsystem function in ops_pci(dev)
util/dtc/flattree.c:
Make devices from the dts be on_mainboard.
If they're plugged in, they shouldn't be in the dts.
mainboard/amd/serengeti/dts:
Add subsystem_vendor and subsystem_device.
Build tested on Serengeti. Getting closer :)
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1045 f3766cd6-281f-0410-b1cd-43a5c92072e9
Add a small collection of PNP enter/exit functions for many Super I/Os.
Use these functions instead of duplicating them for each chip.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1044 f3766cd6-281f-0410-b1cd-43a5c92072e9
Build tested on Serengeti.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1043 f3766cd6-281f-0410-b1cd-43a5c92072e9
I see no reason to have these memory work related debug calls commented out in the code, everyone should know what to locally temporarily add to debug this.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1037 f3766cd6-281f-0410-b1cd-43a5c92072e9
the console banner and the option table will never be updated with more
recent build.h strings.
Thanks to Mart Raudsepp for spotting this oddness.
x86emu doesn't care about the contents of build.h, it just uses build.h
to check whether it is compiled in conjunction with coreboot.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1036 f3766cd6-281f-0410-b1cd-43a5c92072e9
The hardware monitor defaults as per datasheet are 0x0000 / 0, but on
hardware that uses this functionality it seems to be 0x290 / 5 often,
thus use those values in the dts.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1034 f3766cd6-281f-0410-b1cd-43a5c92072e9
up a function prototype.
Fix up #include statements for W83627THG SuperI/O stage2 code.
Use anonymous instead of named unions in struct device.
Point pnp_dev_info members to w83627thg_ops.
Disable UART and keyboard initialization for now.
Add new code in phase3_chip_setup_dev to fill in configuration values
from the dts (code is partially disabled).
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1032 f3766cd6-281f-0410-b1cd-43a5c92072e9
Parts of this patch (southbridge/intel/i82801gx/smi.c) were
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
The rest is
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1031 f3766cd6-281f-0410-b1cd-43a5c92072e9
The build system isn't even using it so far, but if it would the
build would break (and the code wouldn't work for this hardware).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1030 f3766cd6-281f-0410-b1cd-43a5c92072e9
It shouldn't break anything that was working, but I didn't try to fix SuperIOs
that weren't compiling when I started.
Compile tested on
1. amd/dbm690t for ite/it8712f
2. amp/tinygx for ite/it8716f
I'd already updated fintek/f71805 before I realized jetway doesn't compile.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1028 f3766cd6-281f-0410-b1cd-43a5c92072e9
in.
include/device/pnp.h:
Add enable, val, and irq & drq structs.
superio/winbond/w83627hf/superio.c:
Change functions to operate on children.
Add device ID to ops.
Add enables to pnp_dev_info table.
Fill in dts values.
superio/winbond/w83627hf/dts:
Get rid of device number parameters.
Add config parameters so we know when they're set.
device/pnp_device.c:
Allocate devices as children to SuperIO.
mainboard/amd/serengeti/dts:
Move ioport so it's found. (Not its permanent resting place I hope.)
Add enables for KBC, SP1, and HWM to show it off.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1027 f3766cd6-281f-0410-b1cd-43a5c92072e9
/home/rminnich/coreboot-v3/build/coreboot.initram_partiallylinked.o: section .data.rel.ro.local: dual_channel_slew_group_lookup.3242 single_channel_slew_group_lookup.3243
and
/home/rminnich/coreboot-v3/southbridge/intel/i82801gx/smbus.c:34: error: conflicting types for ‘smbus_read_byte’
include/device/smbus.h:56: error: previous declaration of ‘smbus_read_byte’ was here
we are working these. The second is much harder than it seems.
It concerns whether we put i2c devices (i.e. DRAM spd SEEPROMS) in the dts.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1026 f3766cd6-281f-0410-b1cd-43a5c92072e9
Comment out not-yet-supplied initialize_cpus.
Fix missing ; in smbus.c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1025 f3766cd6-281f-0410-b1cd-43a5c92072e9
include/device/path.h
Make path_eq take const path*.
include/device/device.h
Use const with dev_path, dev_id_string, bus_path, find_dev_path,
andalloc_find.
device/device.c
Add functions for tree printing of devs and resources.
Change %p to more useful info.
device/device_util.c
Use const changes from device.h.
lib/stage2.c
Use updated printing functions.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1024 f3766cd6-281f-0410-b1cd-43a5c92072e9
Lots more to do.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1023 f3766cd6-281f-0410-b1cd-43a5c92072e9
It includes an ide option that has to be there, and fixes a CPU test in
Kconfig.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1021 f3766cd6-281f-0410-b1cd-43a5c92072e9
Make statics non-static (we don't do buildrom any more)
Index: northbridge/intel/i945/raminit.c
remove snarf-o that left k8 in (I used wrong script I guess?)
Index: southbridge/intel/i82801gx/stage1_smbus.c
static to global
Index: mainboard/kontron/986lcd-m/stage1.c
Remove functions that have to be in initram.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1020 f3766cd6-281f-0410-b1cd-43a5c92072e9
Index: arch/x86/intel/core2/stage1.c
Initial core2 disable_car and stop_ap
disable_car is wrong but we can fix that tomorrow -- it's core 2 day on friday!
Index: arch/x86/via/stage1.c
Add empty stop_ap()
Index: mainboard/kontron/986lcd-m/stage1_debug.c
Cleanup
Index: mainboard/kontron/986lcd-m/initram.c
Cleanup
Index: mainboard/jetway/j7f2/stage1.c
Remove definition of stop_ap; this belongs in the cpu!
Index: southbridge/intel/i82801gx/libsmbus.c
Fix definition of TIMEOUT (i.e. remove it)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1019 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Uncomment the dbe61a SPD table
* Modify spd_read_byte to support a DIMM SPD address at DIMM_DBE61A that outputs data from dbe61a SPD table instead of dbe61c; approach tip from Marc Jones
* In main() after setting up DBE61C 256MB RAM, run a ram_check, and if that returns a greater than zero verify error count set up 128MB for DBE61A instead
* Tweak the dbe61a SPD table to result in LX MSR values as known to work in Artec v2 branch - this is DBE62/DBE61C values, with density and NUM_COLUMNS halved, and some timings tweaked according to the v2 results.
Now memtest86+ is quite happy on both DBE61C and DBE61A.
Note that it should be better to ram_check in the high memory areas, but that doesn't seem to currently work.
Low memory check seems fine for the immediate time being, as the results appear shifted there as well with the wrong size/timing setup.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Good enough for now.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1018 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1017 f3766cd6-281f-0410-b1cd-43a5c92072e9
Then we can later use it for re-initializing for different SPD without code duplication.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1016 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is in preparation of dbe61a handling addition.
Uses DIMM_DBE61C and DIMM_EMPTY instead of generic DIMM0/DIMM1, and
spd_table_dbe61c instead of spd_table.
Also removes a completely unused smb_devices structure definition.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1015 f3766cd6-281f-0410-b1cd-43a5c92072e9
Will be necessary for DBE61 automatic memory size selection.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1014 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is a complete rewrite of my earlier stack checker proposal.
It works for CAR and RAM, has better abstraction and actually gives us
nice results.
The stack checker is default off due to its rather measurable impact on
boot speed.
Diagnostic messages are printed on first initialization, directly after
RAM init and directly before passing control to the payload. Sample qemu
log is attached. Extract from that log follows:
coreboot-3.0.986 Fri Nov 7 04:04:37 CET 2008 starting...
(console_loglevel=8)
Initial lowest stack is 0x0008fe98
Choosing fallback boot.
[...]
Done RAM init code
After RAM init, lowest stack is 0x0008fe30
Done printk() buffer move
[...]
LAR: load_file_segments: Failed for normal/payload
Before handoff to payload, lowest stack is 0x0008bf50
FATAL: No usable payload found.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1012 f3766cd6-281f-0410-b1cd-43a5c92072e9
