Emulation/switch-coreboot
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Kill v2 leftovers.

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Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1013 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Carl-Daniel Hailfinger 2008-11-13 01:53:55 +00:00
parent cb9db3b6d0
commit 99e68b9345
1 changed files with 0 additions and 2 deletions
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2
arch/x86/intel/core2/stage0.S
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@ -64,7 +64,6 @@ __protected_stage0:
movw %ax, %gs
cache_as_ram:
#if USE_FALLBACK_IMAGE == 1
port80_post(0x20)
@ -129,7 +128,6 @@ clear_mtrrs:
//movl $0x23322332, %eax
xorl %eax, %eax
rep stosl
#endif
/* Enable Cache As RAM mode by disabling cache */
movl %cr0, %eax