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https://github.com/fail0verflow/switch-coreboot.git
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Gigabyte M57SLI compilation is broken in v3. With a small makefile and
dts change, the target compiles again. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1035 f3766cd6-281f-0410-b1cd-43a5c92072e9
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2 changed files with 5 additions and 0 deletions
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@ -21,6 +21,7 @@
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STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
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$(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
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$(src)/arch/x86/resourcemap.c \
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$(src)/arch/x86/stage1_mtrr.c \
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$(src)/arch/x86/amd/model_fxx/dualcore_id.c \
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$(src)/arch/x86/amd/model_fxx/stage1.c \
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@ -55,5 +55,9 @@
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/config/("southbridge/nvidia/mcp55/sata.dts");
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};
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};
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ioport@2e {
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/config/("superio/ite/it8716f/dts");
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com1enable = "1";
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};
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};
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};
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