mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Drop non-working, copy-paste superio.c file (trivial).
The build system isn't even using it so far, but if it would the build would break (and the code wouldn't work for this hardware). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1030 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann
parent
39d6231572
commit
7c960311f9
2 changed files with 1 additions and 217 deletions
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@ -27,7 +27,7 @@ void vt1211_enable_serial(u8 dev, u8 serial, u16 iobase)
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rawpnp_enter_ext_func_mode(dev);
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rawpnp_set_logical_device(dev, serial);
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rawpnp_set_enable(dev, 0);
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rawpnp_set_iobase(dev, 2, (iobase>>2) & 0xff);
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rawpnp_set_iobase(dev, 2, (iobase >> 2) & 0xff);
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rawpnp_set_enable(dev, 1);
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rawpnp_exit_ext_func_mode(dev);
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}
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@ -1,216 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2000 AG Electronics Ltd.
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* Copyright 2003-2004 Linux Networx
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* Copyright 2004 Tyan
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* By LYH change from PC87360
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* Copyright 2007 coresystems GmbH
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*
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* FIXME: This is total hack and slash of v2 code
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <io.h>
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#include <lib.h>
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#include <device/device.h>
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#include <device/pnp.h>
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#include <console.h>
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#include <string.h>
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//#include <bitops.h>
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#include <uart8250.h>
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#include <keyboard.h>
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// #include <pc80/mc146818rtc.h>
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#include <statictree.h>
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#include "w83627hf.h"
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static void pnp_enter_ext_func_mode(struct device * dev)
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{
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outb(0x87, dev->path.pnp.port);
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outb(0x87, dev->path.pnp.port);
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}
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static void pnp_exit_ext_func_mode(struct device * dev)
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{
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outb(0xaa, dev->path.pnp.port);
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}
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static void pnp_write_index(u16 port_base, u8 reg, u8 value)
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{
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outb(reg, port_base);
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outb(value, port_base + 1);
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}
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static u8 pnp_read_index(u16 port_base, u8 reg)
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{
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outb(reg, port_base);
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return inb(port_base + 1);
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}
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static void enable_hwm_smbus(struct device * dev) {
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/* set the pin 91,92 as I2C bus */
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u8 reg, value;
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reg = 0x2b;
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value = pnp_read_config(dev, reg);
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value &= 0x3f;
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pnp_write_config(dev, reg, value);
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}
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static void init_acpi(struct device * dev)
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{
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u8 value = 0x20;
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int power_on = 1;
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#warning Fix CMOS handling
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// get_option(&power_on, "power_on_after_fail");
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pnp_enter_ext_func_mode(dev);
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pnp_write_index(dev->path.pnp.port,7,0x0a);
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value = pnp_read_config(dev, 0xE4);
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value &= ~(3<<5);
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if(power_on) {
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value |= (1<<5);
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}
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pnp_write_config(dev, 0xE4, value);
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pnp_exit_ext_func_mode(dev);
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}
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static void init_hwm(u16 base)
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{
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u8 reg, value;
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int i;
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unsigned hwm_reg_values[] = {
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/* reg, mask, data */
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0x40, 0xff, 0x81, /* start HWM */
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0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */
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0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */
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0x4e, 0x80, 0x00,
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0x43, 0x00, 0xff,
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0x44, 0x00, 0x3f,
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0x4c, 0xbf, 0x18,
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0x4d, 0xff, 0x80 /* turn off beep */
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};
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for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
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reg = hwm_reg_values[i];
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value = pnp_read_index(base, reg);
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value &= 0xff & hwm_reg_values[i+1];
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value |= 0xff & hwm_reg_values[i+2];
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printk(BIOS_SPEW, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value);
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pnp_write_index(base, reg, value);
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}
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}
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static void w83627hf_init(struct device * dev)
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{
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struct superio_winbond_w83627hf_dts_config *conf;
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struct resource *res0, *res1;
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struct pc_keyboard keyboard;
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#if 1
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printk(BIOS_ERR, "dummy init XXXX\n");
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#endif
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if (!dev->enabled) {
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return;
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}
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conf = dev->device_configuration;
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switch(dev->path.pnp.device) {
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case W83627HF_SP1:
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res0 = find_resource(dev, PNP_IDX_IO0);
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#warning init_uart8250
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//init_uart8250(res0->base, &conf->com1);
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break;
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case W83627HF_SP2:
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res0 = find_resource(dev, PNP_IDX_IO0);
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#warning init_uart8250
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//init_uart8250(res0->base, &conf->com2);
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break;
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case W83627HF_KBC:
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res0 = find_resource(dev, PNP_IDX_IO0);
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res1 = find_resource(dev, PNP_IDX_IO1);
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init_pc_keyboard(res0->base, res1->base, &keyboard);
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break;
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case W83627HF_HWM:
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res0 = find_resource(dev, PNP_IDX_IO0);
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#define HWM_INDEX_PORT 5
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init_hwm(res0->base + HWM_INDEX_PORT);
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break;
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case W83627HF_ACPI:
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init_acpi(dev);
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break;
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}
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}
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void w83627hf_pnp_set_resources(struct device * dev)
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{
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pnp_enter_ext_func_mode(dev);
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pnp_set_resources(dev);
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pnp_exit_ext_func_mode(dev);
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}
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void w83627hf_pnp_enable_resources(struct device * dev)
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{
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pnp_enter_ext_func_mode(dev);
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pnp_enable_resources(dev);
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switch(dev->path.pnp.device) {
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case W83627HF_HWM:
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printk(BIOS_DEBUG, "w83627hf hwm smbus enabled\n");
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enable_hwm_smbus(dev);
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break;
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}
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pnp_exit_ext_func_mode(dev);
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}
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void w83627hf_pnp_enable(struct device * dev)
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{
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if (!dev->enabled) {
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pnp_enter_ext_func_mode(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_exit_ext_func_mode(dev);
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}
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}
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static void phase2_setup_scan_bus(struct device *dev);
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struct device_operations w83627hf_ops = {
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.phase2_setup_scan_bus = phase2_setup_scan_bus,
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.phase4_read_resources = pnp_read_resources,
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.phase4_set_resources = w83627hf_pnp_set_resources,
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.phase4_enable_disable = w83627hf_pnp_enable_resources,
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.phase5_enable_resources = w83627hf_pnp_enable,
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.phase6_init = w83627hf_init,
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};
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static struct pnp_info pnp_dev_info[] = {
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{ &w83627hf_ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
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{ &w83627hf_ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
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{ &w83627hf_ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
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{ &w83627hf_ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
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// No 4 { 0,},
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{ &w83627hf_ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
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{ &w83627hf_ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
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{ &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
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{ &w83627hf_ops, W83627HF_GPIO2, },
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{ &w83627hf_ops, W83627HF_GPIO3, },
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{ &w83627hf_ops, W83627HF_ACPI, },
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{ &w83627hf_ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
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};
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static void phase2_setup_scan_bus(struct device *dev)
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{
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pnp_enable_devices(dev, &w83627hf_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
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}
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