And update the string length. Many thanks to Mathias Krause for spotting this!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1159 f3766cd6-281f-0410-b1cd-43a5c92072e9
Base 16 number printing used digits[33] instead of the more readable 'x'
for the "0x" prefix. That means you have to look up an array just to
find out what the code does. Change it.
We already write "<NULL>" if printk gets a NULL pointer as string
argument. Introduce "<near NULL>" for string arguments with addresses
below 0x400. This error happened in the past when dereferencing a struct
member with a string and the struct had the address NULL.
Check if all to-be-printed characters in the string are indeed
printable. The idea is to catch garbage strings from stray pointers and
print "<non-ASCII characters>" instead.
If a string contains characters outside classic ASCII printable stuff,
this will trigger. An example would be characters with diacritic marks
like äöüéăçőč.
Then again, I don't see localized versions of coreboot on the horizon.
Maybe for payloads, but not for coreboot itself.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1158 f3766cd6-281f-0410-b1cd-43a5c92072e9
due to integer rounding errors. Previously, the formula was:
speed = 2 * (10000/spd_value)
For spd_value=60 this means speed = 2 * 166 = 332, which is less than
333 and coreboot died saying RAM was incompatible. The new formula is:
speed = 20000 / spd_value
For spd_value=60, speed=333, which is fine.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Mart writes:
Tested on ThinCan DBE63 to fix the issue of 333 > 332 comparison for RAM
modules I had problems with before due to bailing out in the
overclocking check.
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1157 f3766cd6-281f-0410-b1cd-43a5c92072e9
This patch makes it possible for Option ROMs to access devices
other than the one YABEL is running for. This is needed for some
onboard Graphics Cards Option ROMs.
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Tested and Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1155 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Tested and Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1154 f3766cd6-281f-0410-b1cd-43a5c92072e9
It requires a flag (CONFIG_SCAN_BUILD) to be set, and then
$ scan-build make
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1146 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is a potentially good pointer to where someone can take this.
While startup was working, BSP now explodes once the AP stops, while
BSP is doing startup IPI loop send #2. The code needs to be hardened; I
think use of the shared variables would really make it much more solid.
This would be a good undergrad student project if someone is looking for one.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1145 f3766cd6-281f-0410-b1cd-43a5c92072e9
debugging in, using locations 0 and _secondary_start as POST.
Calling from initram did not work out, as we have to disable_car in initram
to make such a call work (on core2). For now,
I am calling this from stage1_phase 3, before stage2 is called. But that
has increased the code size of stage1, which is not a great idea.
What I am thinking we ought to do: call this from stage2, before phase 1,
so that CPUs are nice and set up and quiet.
Provide phase2 with an SMP-safe printk.
This is here so others may see it and correct my work. The good news is
that SMP startup on core2 on v3 is now starting to go. But the better news
is that the way this is working is pretty generic and ought to apply to
much more than just core2.
To really look at object you might want to get ndisasm.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1143 f3766cd6-281f-0410-b1cd-43a5c92072e9
it in the v2 tree as well. Requires the yabel-prereq.diff patch in order to
work in v2.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1141 f3766cd6-281f-0410-b1cd-43a5c92072e9
*_SUPPORT options with NO_*_SUPPORT options. This means that you have
to specify that you want a smaller BIOS, otherwise you get full
functionality.
HyperTransport is the only exception for a couple of reasons. HT
requires a mainboard.h file which not all mainboards have, and it's
less likely to be "plugged in" to a board that doesn't have some
onboard HT.
It also fixes a trivial typo in Kconfig (paylaod -> payload)
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1140 f3766cd6-281f-0410-b1cd-43a5c92072e9
people can suggest what's wrong.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1139 f3766cd6-281f-0410-b1cd-43a5c92072e9
The reset value for NAND timings is the slowest possible for Flash interface.
Implement optionally setting it to a different value inside the NAND device.
Set it to appropriate values for Artec Group DBE61 and DBE62.
This results in a roughly two times quicker read time as measured by hdparm
for these boards.
Because we can not cast to southbridge_amd_cs5536_nand_config if the board dts
does not have an entry for the NAND device, this change proposes a method for
reasonably clean way to only optionally compile in support for certain devices:
If a board wants to support an optional device, its Kconfig entry can select
that configuration. If it's optional even across the same board, it can expose
a subconfig option of the board, that describes it and if chosen selects the
device config. The source code for that device is conditionally compiled only
if the Kconfig option gets enabled by the configuration for the board.
A requirement is that if the board configuration can enable a device, it is
contained in the boards dts file as well.
A perhaps better long-term alternative for this could be making dtc generate
preprocessor definitions for each device_configuration struct that it creates.
Then the source code file is always enabled, but that file can be wrapped
around a simple #ifdef check in its entirety.
Conversion to the alternative approach from the short-term Kconfig approach
proposed here should be relatively easy, as to not block inclusion of the
Kconfig approach in the short term.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1138 f3766cd6-281f-0410-b1cd-43a5c92072e9
I can still get to linux but core1 is not working.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1137 f3766cd6-281f-0410-b1cd-43a5c92072e9
adaption of the v2 code, with significant cleanup and
simplification. It also works in CAR mode, and has no .bss or .data
usage. It provides for a way to provide AP POST codes to the BSP.
Since one common file with amd changed (lapic.h) I have build-tested this
against serengeti and it is fine.
It builds and I'll be testing it as soon as I can find the power supply for
the kontron (it got "borrowed").
Index: arch/x86/intel/core2/init_cpus.c
new file. Basically an adaptation of the v2 code to v3. All global variables
removed. One big change to note: there is a stack struct, and the
parameters to the secondary_start are struct members. Thus the BSP
can watch the AP, and, neater, the AP can POST to a shared variable
and the BSP can see how far it got.
Index: arch/x86/secondary.S
.S startup for AP.
Index: arch/x86/Kconfig
Delete a dependency.
Index: northbridge/intel/i945/reset_test.c
Add real cold boot detection.
Index: mainboard/kontron/986lcd-m/Makefile
Add some new build files.
Index: mainboard/kontron/986lcd-m/stage1.c
Get rid of ' in #warning that confused some tool.
Index: mainboard/kontron/986lcd-m/initram.c
Call init_cpus.
Index: mainboard/kontron/Kconfig
Turn off SMM for now.
Index: include/arch/x86/lapic.h
Correct a static inline declaration.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1136 f3766cd6-281f-0410-b1cd-43a5c92072e9
.S into the source file list, for reasons unknown, gcc only builds a .o
with the .S symbols/code in it; all the .c bits disappear.
So, a few changes:
1. add a rule for secondary.o, we're going to need it.
I like the fact that adding a .S file is inconvenient. Good.
Adding assembly should be hard.
2. Make two steps to initram .o building: first, the .c files, then any
extra .o files as specified by the mainboard Makefile
I realize this is a bit ugly, if there is a better solution, I'll take it.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1135 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1134 f3766cd6-281f-0410-b1cd-43a5c92072e9
2 size calculations.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1133 f3766cd6-281f-0410-b1cd-43a5c92072e9
does not compile, but this needed fixing anyway.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1132 f3766cd6-281f-0410-b1cd-43a5c92072e9
that has already been done by the BSP. For single processor systems the CPU
flag is always 0, BSP. This code also moves the AP stop for K8 mainboards to
after memory setup so the AP's MTRRs can be setup to match system memory.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1129 f3766cd6-281f-0410-b1cd-43a5c92072e9
stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
It also sets all system memory to WriteBack cached and sets the ROM
area to cached.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1128 f3766cd6-281f-0410-b1cd-43a5c92072e9
be passed in registers. This is good for size and speed but not good when
we call a C function from asm. Force stage1_phase1 to use stdcall and get
variables off the stack.
Note that I didn't change stage1_phase3 because it doesn't use any
variables.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1127 f3766cd6-281f-0410-b1cd-43a5c92072e9
A NAND device may never be mapped above 0xEFFFFFFF, as these addresses never reach
the NAND controller. Only NAND controller, as the only DIVIL component that is
allowed to be memory mapped, is affected - other Geode LX and CS5536 peripherals
(that are separate GLIU devices outside DIVIL component) can use addresses above
that limit (see in-code comment for details).
In combination with a new VSA2 version 1.02 or newer, this makes NAND flash
finally work in coreboot v3.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Signed-off-by: Anti Sullin <anti.sullin@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1125 f3766cd6-281f-0410-b1cd-43a5c92072e9
Trivial: constant currently not used anywhere.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1124 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Maggie Li <maggie.li@amd.com>
Reviewed-by: Zheng Bao <Zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1123 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1122 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1121 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1120 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Copying of files from other mainboards as a starting point:
amd/db800/Makefile
artecgroup/dbe62/cmos.layout
artecgroup/dbe62/dts
amd/db800/initram.c
artecgroup/dbe61/irq_tables.h
artecgroup/dbe62/stage1
* Kconfig integration. Behind CONFIG_EXPERIMENTAL for now, as the board is not in the market yet.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1119 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1117 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1116 f3766cd6-281f-0410-b1cd-43a5c92072e9
SPD_MIN_RAS_TO_CAS_DELAY is already set earlier in the list, so the alternative
constant tRCD in the end has no effect in the memory algorithm - remove them.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1115 f3766cd6-281f-0410-b1cd-43a5c92072e9
The device infrastructure already has an enabled bit, so we don't need to duplicate it in the current form.
cs5536.c:ide_init() is phase6_init, which is called only if the device is enabled, so if the device doesn't
exist, or the mainboard dts says "disabled;" for it, the init is not done and an extra conditional is not
necessary.
Adapt all cs5536 using mainboards to it (removing enable_ide variable) - artecgroup/dbe6[12] gets the whole
IDE device removed, which results in the ide_init() code not being ran as before (before it was called but
early return from enable_ide == 0, now it won't be called in the first place).
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1114 f3766cd6-281f-0410-b1cd-43a5c92072e9
This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better.
It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late
before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2
before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it
enabled in VSA2.
It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch,
but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the
VSA2 bug suggests something further will still need fixing. There are also more potential opportunities
to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup
actually works right in the current form.
Also corrected the documentation of ide_init() to match current reality.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1113 f3766cd6-281f-0410-b1cd-43a5c92072e9
