Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1053 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1052 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1051 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1050 f3766cd6-281f-0410-b1cd-43a5c92072e9
Make statics non-static (we don't do buildrom any more)
Index: northbridge/intel/i945/raminit.c
remove snarf-o that left k8 in (I used wrong script I guess?)
Index: southbridge/intel/i82801gx/libsmbus.c
Corrections (minor)
Index: southbridge/intel/i82801gx/stage1_smbus.c
static to global
Index: mainboard/kontron/986lcd-m/stage1_debug.c
don't include statictree.c
Index: mainboard/kontron/986lcd-m/stage1.c
Remove functions that have to be in initram.
Index: mainboard/kontron/986lcd-m/initram.c
Add functions. This is all about splitting auto.c into stage1 and initram.
stage1 is very small and limited.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1049 f3766cd6-281f-0410-b1cd-43a5c92072e9
pci_set_resources. There is no matching pci_bus_set_resources, so it's
confusing to see the dev function in the bus structures.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
device/pci_device.c:
Only update IDs if:
- The device is on the mainboard
- The device has a Vendor ID and Device ID
- The device has a set_subsystem function in ops_pci(dev)
util/dtc/flattree.c:
Make devices from the dts be on_mainboard.
If they're plugged in, they shouldn't be in the dts.
mainboard/amd/serengeti/dts:
Add subsystem_vendor and subsystem_device.
Build tested on Serengeti. Getting closer :)
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1045 f3766cd6-281f-0410-b1cd-43a5c92072e9
I see no reason to have these memory work related debug calls commented out in the code, everyone should know what to locally temporarily add to debug this.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1037 f3766cd6-281f-0410-b1cd-43a5c92072e9
Parts of this patch (southbridge/intel/i82801gx/smi.c) were
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
The rest is
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1031 f3766cd6-281f-0410-b1cd-43a5c92072e9
in.
include/device/pnp.h:
Add enable, val, and irq & drq structs.
superio/winbond/w83627hf/superio.c:
Change functions to operate on children.
Add device ID to ops.
Add enables to pnp_dev_info table.
Fill in dts values.
superio/winbond/w83627hf/dts:
Get rid of device number parameters.
Add config parameters so we know when they're set.
device/pnp_device.c:
Allocate devices as children to SuperIO.
mainboard/amd/serengeti/dts:
Move ioport so it's found. (Not its permanent resting place I hope.)
Add enables for KBC, SP1, and HWM to show it off.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1027 f3766cd6-281f-0410-b1cd-43a5c92072e9
/home/rminnich/coreboot-v3/build/coreboot.initram_partiallylinked.o: section .data.rel.ro.local: dual_channel_slew_group_lookup.3242 single_channel_slew_group_lookup.3243
and
/home/rminnich/coreboot-v3/southbridge/intel/i82801gx/smbus.c:34: error: conflicting types for ‘smbus_read_byte’
include/device/smbus.h:56: error: previous declaration of ‘smbus_read_byte’ was here
we are working these. The second is much harder than it seems.
It concerns whether we put i2c devices (i.e. DRAM spd SEEPROMS) in the dts.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1026 f3766cd6-281f-0410-b1cd-43a5c92072e9
Comment out not-yet-supplied initialize_cpus.
Fix missing ; in smbus.c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1025 f3766cd6-281f-0410-b1cd-43a5c92072e9
Lots more to do.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1023 f3766cd6-281f-0410-b1cd-43a5c92072e9
It includes an ide option that has to be there, and fixes a CPU test in
Kconfig.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1021 f3766cd6-281f-0410-b1cd-43a5c92072e9
Make statics non-static (we don't do buildrom any more)
Index: northbridge/intel/i945/raminit.c
remove snarf-o that left k8 in (I used wrong script I guess?)
Index: southbridge/intel/i82801gx/stage1_smbus.c
static to global
Index: mainboard/kontron/986lcd-m/stage1.c
Remove functions that have to be in initram.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1020 f3766cd6-281f-0410-b1cd-43a5c92072e9
Index: arch/x86/intel/core2/stage1.c
Initial core2 disable_car and stop_ap
disable_car is wrong but we can fix that tomorrow -- it's core 2 day on friday!
Index: arch/x86/via/stage1.c
Add empty stop_ap()
Index: mainboard/kontron/986lcd-m/stage1_debug.c
Cleanup
Index: mainboard/kontron/986lcd-m/initram.c
Cleanup
Index: mainboard/jetway/j7f2/stage1.c
Remove definition of stop_ap; this belongs in the cpu!
Index: southbridge/intel/i82801gx/libsmbus.c
Fix definition of TIMEOUT (i.e. remove it)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1019 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Uncomment the dbe61a SPD table
* Modify spd_read_byte to support a DIMM SPD address at DIMM_DBE61A that outputs data from dbe61a SPD table instead of dbe61c; approach tip from Marc Jones
* In main() after setting up DBE61C 256MB RAM, run a ram_check, and if that returns a greater than zero verify error count set up 128MB for DBE61A instead
* Tweak the dbe61a SPD table to result in LX MSR values as known to work in Artec v2 branch - this is DBE62/DBE61C values, with density and NUM_COLUMNS halved, and some timings tweaked according to the v2 results.
Now memtest86+ is quite happy on both DBE61C and DBE61A.
Note that it should be better to ram_check in the high memory areas, but that doesn't seem to currently work.
Low memory check seems fine for the immediate time being, as the results appear shifted there as well with the wrong size/timing setup.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Good enough for now.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1018 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1017 f3766cd6-281f-0410-b1cd-43a5c92072e9
Then we can later use it for re-initializing for different SPD without code duplication.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1016 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is in preparation of dbe61a handling addition.
Uses DIMM_DBE61C and DIMM_EMPTY instead of generic DIMM0/DIMM1, and
spd_table_dbe61c instead of spd_table.
Also removes a completely unused smb_devices structure definition.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1015 f3766cd6-281f-0410-b1cd-43a5c92072e9
Why? Because the board doesn't use ide support. So you can't compile that in, it's not in the dts.
the mainboard Makefile picks the southbridge .c's to use.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1009 f3766cd6-281f-0410-b1cd-43a5c92072e9
and keep getting called away ... waiting for 1024 procs takes patience!)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1008 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1007 f3766cd6-281f-0410-b1cd-43a5c92072e9
Also upper-cases the hex in lpc_serirq_polarity as all other Geode boards have it as such,
and remove parts of the commented out reference v2 setup block that should be handled by
this change now.
The USB power handling setting is meant to get the second pair of USB ports to be powered
on, as this changed done by Ron to DBE62 fixed DBE62's third and fourth USB port to be usable.
Oddly the USB power handling setting also makes memtest work, while without it memtest gets
unexpected interrupt halts right after it loads up.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1006 f3766cd6-281f-0410-b1cd-43a5c92072e9
Changes the interrupt router location to what all other Geode board ports are using, and
doesn't exclusively devote any IRQs for PCI usage, as no other Geode board does so.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1005 f3766cd6-281f-0410-b1cd-43a5c92072e9
cpu setup is nonexistent. No car either. Work remains ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1000 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@999 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@998 f3766cd6-281f-0410-b1cd-43a5c92072e9
This actually starts to get compile errors, instead of config errors.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@994 f3766cd6-281f-0410-b1cd-43a5c92072e9
Lots of wrong stuff here, but a lot of stuff is right. I am looking for
all the help I can get.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@992 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Marc Jones <marcj303@yahoo.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@986 f3766cd6-281f-0410-b1cd-43a5c92072e9
Modify chipset_flash_setup to support enabling NAND flash on other locations
than CS0, by making enable_ide_nand_flash have a non-boolean meaning where zero
means no NAND (IDE), and 1 through 4 gives the one-based chip select array
location (so 1 means CS0, 2 means CS1, 3 means CS2 and 4 means CS3, as chip
select notation is zero-based).
This loses the code for supporting more than one NAND chip select or different
ones than FLASH_MEM_4K, but these couldn't be supported before anyway, because
that is board specific, but the supporting structure was a static const struct
in generic southbridge specific code.
This support should be instead implemented via the device tree dts files.
Enables NAND on ArtecGroup DBE61 and DBE62 on CS1, as that's where it is.
The end result is that these mainboards can now boot off of NAND with FILO
without local modifications to the previously existing southbridge specific
static const struct that had no chance of being upstreamed as it would break
all other CS5536 NAND boards that have it on CS0.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@985 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@976 f3766cd6-281f-0410-b1cd-43a5c92072e9
Make cmos.layout work with incomprehensible tool -- just turn off checksums.
Add static.c to list of files covered by kscope
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@975 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@974 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@973 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@972 f3766cd6-281f-0410-b1cd-43a5c92072e9
mainboard.h -- we need a better way to do this. We should not have to specify address bits in
this way. But it is not as easy a problem as it seems.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@969 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@968 f3766cd6-281f-0410-b1cd-43a5c92072e9
Does not yet build
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@967 f3766cd6-281f-0410-b1cd-43a5c92072e9
Most substantive change is getting rid of 'initialized', which was only
ever needed in v2 due to an implementation mistake.
With Uwe's comments taken into account,
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@961 f3766cd6-281f-0410-b1cd-43a5c92072e9
