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https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Yes, starting to build.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@998 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
adc163d08f
commit
ea391ee4b6
3 changed files with 85 additions and 80 deletions
2
Kconfig
2
Kconfig
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@ -120,6 +120,8 @@ config SOUTHBRIDGE_INTEL_I82801GX
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# Super I/Os:
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config SUPERIO_WINBOND_W83627HF
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boolean
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config SUPERIO_WINBOND_W83627THG
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boolean
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config SUPERIO_FINTEK_F71805F
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boolean
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config SUPERIO_ITE_IT8716F
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@ -31,7 +31,7 @@ u8 rawpnp_read_config(u16 port, u8 reg);
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void rawpnp_set_logical_device(u16 port, u8 ldn);
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void rawpnp_set_enable(u16 port, int enable);
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void rawpnp_set_iobase(u16 port, u8 index, u16 iobase);
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void rawpnp_set_irq(u16 port, unsigned index, unsigned irq);
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/* Primitive pnp resource manipulation */
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void pnp_write_config(struct device * dev, u8 reg, u8 value);
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u8 pnp_read_config(struct device * dev, u8 reg);
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@ -24,12 +24,15 @@
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#include <lib.h>
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#include <console.h>
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#include <device/device.h>
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#include <device/pnp.h>
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#include <cpu.h>
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#include <device/pci.h>
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#include <string.h>
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#include <msr.h>
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#include <io.h>
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#include <uart8250.h>
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#include <arch/x86/msr.h>
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#include <arch/x86/lapic.h>
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#include "superio/winbond/w83627thg/w83627thg.h"
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@ -111,91 +114,93 @@ static void ich7_enable_lpc(void)
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*/
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static void early_superio_config_w83627thg(void)
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{
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u32 dev;
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u16 port;
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u8 ldn;
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dev=PNP_DEV(0x2e, W83627THG_SP1);
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pnp_enter_ext_func_mode(dev);
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port = 0x2e;
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ldn = W83627THG_SP1;
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rawpnp_enter_ext_func_mode(port);
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rawpnp_set_logical_device(port, ldn);
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rawpnp_set_enable(port, 0);
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rawpnp_set_iobase(port, PNP_IDX_IO0, 0x3f8);
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rawpnp_set_irq(port, PNP_IDX_IRQ0, 4);
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rawpnp_set_enable(port, 1);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
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pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
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pnp_set_enable(dev, 1);
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ldn = W83627THG_SP2;
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rawpnp_set_logical_device(port, ldn);
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rawpnp_set_enable(port, 0);
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rawpnp_set_iobase(port, PNP_IDX_IO0, 0x2f8);
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rawpnp_set_irq(port, PNP_IDX_IRQ0, 3);
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// rawpnp_write_config(dev, 0xf1, 4); // IRMODE0
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rawpnp_set_enable(port, 1);
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dev=PNP_DEV(0x2e, W83627THG_SP2);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
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pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
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// pnp_write_config(dev, 0xf1, 4); // IRMODE0
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pnp_set_enable(dev, 1);
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ldn = W83627THG_KBC;
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rawpnp_set_logical_device(port, ldn);
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rawpnp_set_enable(port, 0);
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rawpnp_set_iobase(port, PNP_IDX_IO0, 0x60);
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rawpnp_set_iobase(port, PNP_IDX_IO1, 0x64);
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// rawpnp_write_config(port, 0xf0, 0x82);
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rawpnp_set_enable(port, 1);
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dev=PNP_DEV(0x2e, W83627THG_KBC);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
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pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
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// pnp_write_config(dev, 0xf0, 0x82);
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pnp_set_enable(dev, 1);
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ldn = W83627THG_GAME_MIDI_GPIO1;
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rawpnp_set_logical_device(port, ldn);
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rawpnp_set_enable(port, 0);
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rawpnp_write_config(port, 0xf5, 0xff); // invert all GPIOs
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rawpnp_set_enable(port, 1);
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dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs
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pnp_set_enable(dev, 1);
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ldn = W83627THG_GPIO2;
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rawpnp_set_logical_device(port, ldn);
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rawpnp_set_enable(port, 1); // Just enable it
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dev=PNP_DEV(0x2e, W83627THG_GPIO2);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 1); // Just enable it
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ldn = W83627THG_GPIO3;
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rawpnp_set_logical_device(port, ldn);
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rawpnp_set_enable(port, 0);
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rawpnp_write_config(port, 0xf0, 0xfb); // GPIO bit 2 is output
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rawpnp_write_config(port, 0xf1, 0x00); // GPIO bit 2 is 0
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rawpnp_write_config(port, 0x30, 0x03); // Enable GPIO3+4. rawpnp_set_enable is not sufficient
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dev=PNP_DEV(0x2e, W83627THG_GPIO3);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
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pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
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pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
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ldn = W83627THG_FDC;
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rawpnp_set_logical_device(port, ldn);
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rawpnp_set_enable(port, 0);
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dev=PNP_DEV(0x2e, W83627THG_FDC);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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ldn = W83627THG_PP;
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rawpnp_set_logical_device(port, ldn);
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rawpnp_set_enable(port, 0);
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dev=PNP_DEV(0x2e, W83627THG_PP);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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rawpnp_exit_ext_func_mode(port);
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pnp_exit_ext_func_mode(dev);
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port = 0x2e;
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ldn = W83627THG_SP1;
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rawpnp_enter_ext_func_mode(port);
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dev=PNP_DEV(0x4e, W83627THG_SP1);
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pnp_enter_ext_func_mode(dev);
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rawpnp_set_logical_device(port, ldn); // Set COM3 to sane non-conflicting values
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rawpnp_set_enable(port, 0);
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rawpnp_set_iobase(port, PNP_IDX_IO0, 0x3e8);
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rawpnp_set_irq(port, PNP_IDX_IRQ0, 11);
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rawpnp_set_enable(port, 1);
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pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8);
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pnp_set_irq(dev, PNP_IDX_IRQ0, 11);
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pnp_set_enable(dev, 1);
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ldn = W83627THG_SP2;
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rawpnp_set_logical_device(port, ldn); // Set COM4 to sane non-conflicting values
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rawpnp_set_enable(port, 0);
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rawpnp_set_iobase(port, PNP_IDX_IO0, 0x2e8);
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rawpnp_set_irq(port, PNP_IDX_IRQ0, 10);
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rawpnp_set_enable(port, 1);
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dev=PNP_DEV(0x4e, W83627THG_SP2);
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pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8);
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pnp_set_irq(dev, PNP_IDX_IRQ0, 10);
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pnp_set_enable(dev, 1);
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ldn = W83627THG_FDC;
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rawpnp_set_logical_device(port, ldn);
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rawpnp_set_enable(port, 0);
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dev=PNP_DEV(0x4e, W83627THG_FDC);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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ldn = W83627THG_PP;
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rawpnp_set_logical_device(port, ldn);
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rawpnp_set_enable(port, 0);
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dev=PNP_DEV(0x4e, W83627THG_PP);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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ldn = W83627THG_KBC;
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rawpnp_set_logical_device(port, ldn);
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rawpnp_set_enable(port, 0);
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rawpnp_set_iobase(port, PNP_IDX_IO0, 0x00);
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rawpnp_set_iobase(port, PNP_IDX_IO1, 0x00);
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dev=PNP_DEV(0x4e, W83627THG_KBC);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
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pnp_set_iobase(dev, PNP_IDX_IO1, 0x00);
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pnp_exit_ext_func_mode(dev);
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rawpnp_exit_ext_func_mode(port);
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}
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static void rcba_config(void)
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@ -231,8 +236,8 @@ static void rcba_config(void)
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static void early_ich7_init(void)
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{
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uint8_t reg8;
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uint32_t reg32;
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u8 reg8;
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u32 reg32;
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// program secondary mlt XXX byte?
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pci_conf1_write_config8(PCI_BDF(0, 0x1e, 0), 0x1b, 0x20);
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@ -285,24 +290,22 @@ static void early_ich7_init(void)
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#warning need to fix up hardware_stage1 and move parts to initram.c
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void hardware_stage1(void)
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{
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void early_superio_config_w83627thg(void);
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void ich7_enable_lpc(void);
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int boot_mode = 0;
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if (bist == 0) {
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enable_lapic();
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}
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enable_lapic();
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ich7_enable_lpc();
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early_superio_config_w83627thg();
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/* Set up the console */
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uart_init();
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#warning need to know how to call uart8250_init
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// uart8250_init();
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console_init();
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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}
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void mainboard_pre_payload(void)
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{
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banner(BIOS_DEBUG, "mainboard_pre_payload: done");
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