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Fewer errors. The weird part: I had to move all the i82801gx south files to be compiled to the mainboard.

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Why? Because the board doesn't use ide support. So you can't compile that in, it's not in the dts. 
the mainboard Makefile picks the southbridge .c's to use. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1009 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-11-12 23:09:42 +00:00
parent f37c28c24b
commit d83abdaf6f
12 changed files with 59 additions and 52 deletions
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12
mainboard/kontron/986lcd-m/Makefile
View file

@ -28,6 +28,18 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/intel/i945/raminit.c \
STAGE2_CHIPSET_SRC=\
$(src)/southbridge/intel/i82801gx/ac97.c \
$(src)/southbridge/intel/i82801gx/lpc.c \
$(src)/southbridge/intel/i82801gx/nic.c \
$(src)/southbridge/intel/i82801gx/pci.c \
$(src)/southbridge/intel/i82801gx/pcie.c \
$(src)/southbridge/intel/i82801gx/sata.c \
$(src)/southbridge/intel/i82801gx/smbus.c \
$(src)/southbridge/intel/i82801gx/usb_ehci.c \
$(src)/southbridge/intel/i82801gx/usb.c \
$(src)/southbridge/intel/i82801gx/watchdog.c
# $(src)/southbridge/intel/i82801gx/libsmbus.c \
STAGE2_MAINBOARD_SRC =

7
mainboard/kontron/986lcd-m/dts
View file

@ -181,6 +181,13 @@ end
pci@1f,0{/* which ich? */
/config/("southbridge/intel/i82801gx/ich7m_dh_lpc.dts");
};
pci@1f,2{
/config/("southbridge/intel/i82801gx/sata.dts");
};
pci@1f,3{
/config/("southbridge/intel/i82801gx/smbus.dts");
};
};
ioport@2e {
/config/("superio/winbond/w83627thg/dts");

35
northbridge/intel/i945/northbridge.c
View file

@ -28,7 +28,7 @@
#include <config.h>
#include "i945.h"
static void ram_resource(struct device * dev, unsigned long index, unsigned long basek,
static void i945_ram_resource(struct device * dev, unsigned long index, unsigned long basek,
unsigned long sizek)
{
struct resource *resource;
@ -40,7 +40,7 @@ static void ram_resource(struct device * dev, unsigned long index, unsigned long
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void pci_domain_read_resources(struct device * dev)
static void I945_pci_domain_read_resources(struct device * dev)
{
struct resource *resource;
@ -90,7 +90,7 @@ static u32 find_pci_tolm(struct bus *bus)
return tolm;
}
static void pci_domain_set_resources(struct device * dev)
static void I945_pci_domain_set_resources(struct device * dev)
{
u32 pci_tolm;
u8 tolud, reg8;
@ -152,22 +152,22 @@ static void pci_domain_set_resources(struct device * dev)
/* The following needs to be 2 lines, otherwise the second
* number is always 0
*/
printk(BIOS_INFO, "Available memory: %dK", tomk);
printk(BIOS_INFO, " (%dM)\n", (tomk >> 10));
printk(BIOS_INFO, "Available memory: %lldK", tomk);
printk(BIOS_INFO, " (%lldM)\n", (tomk >> 10));
tolmk = tomk;
/* Report the memory regions */
ram_resource(dev, 3, 0, 640);
ram_resource(dev, 4, 768, (tolmk - 768));
i945_ram_resource(dev, 3, 0, 640);
i945_ram_resource(dev, 4, 768, (tolmk - 768));
if (tomk > 4 * 1024 * 1024) {
ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
i945_ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
}
assign_resources(&dev->link[0]);
}
static unsigned int pci_domain_scan_bus(struct device * dev, unsigned int max)
static unsigned int i945_pci_domain_scan_bus(struct device * dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
/* TODO We could determine how many PCIe busses we need in
@ -176,15 +176,16 @@ static unsigned int pci_domain_scan_bus(struct device * dev, unsigned int max)
return max;
}
#warning get number of 945 pci domain ops
struct device_operations i945_pci_domain_ops = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_INTEL,
.device = anumber}}},
.device = 0x6789}}},
.constructor = default_device_constructor,
.reset_bus = pci_bus_reset,
.phase3_scan = pci_domain_scan_bus,
.phase4_read_resources = pci_domain_read_resources,
.phase4_set_resources = pci_domain_set_resources,
.phase3_scan = i945_pci_domain_scan_bus,
.phase4_read_resources = I945_pci_domain_read_resources,
.phase4_set_resources = I945_pci_domain_set_resources,
.phase5_enable_resources = enable_childrens_resources,
.phase6_init = NULL,
.ops_pci = &pci_dev_ops_pci,
@ -208,8 +209,8 @@ static void mc_read_resources(struct device * dev)
resource->flags =
IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08x-0x%08x.\n",
resource->base, (resource->base + resource->size));
printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08llx.\n",
(u64) resource->base, (u64) (resource->base + resource->size));
}
static void mc_set_resources(struct device * dev)
@ -260,7 +261,7 @@ static void cpu_bus_noop(struct device * dev)
}
#warning get a number of the 945 mc
struct device_operations i945_mc_ops = {
struct device_operations i945_cpu_ops = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x1233}}},
@ -268,6 +269,6 @@ struct device_operations i945_mc_ops = {
.phase4_read_resources = cpu_bus_noop,
.phase4_set_resources = cpu_bus_noop,
.phase5_enable_resources = cpu_bus_noop,
.phase6_init = Ncpu_bus_initULL,
.phase6_init = cpu_bus_init,
.ops_pci = &intel_pci_ops,
};

12
southbridge/intel/i82801gx/Makefile
View file

@ -24,18 +24,6 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y)
STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82801gx/i82801gx.c
STAGE2_CHIPSET_SRC += \
$(src)/southbridge/intel/i82801gx/ac97.c \
$(src)/southbridge/intel/i82801gx/ide.c \
$(src)/southbridge/intel/i82801gx/lpc.c \
$(src)/southbridge/intel/i82801gx/nic.c \
$(src)/southbridge/intel/i82801gx/pci.c \
$(src)/southbridge/intel/i82801gx/pcie.c \
$(src)/southbridge/intel/i82801gx/sata.c \
$(src)/southbridge/intel/i82801gx/smbus.c \
$(src)/southbridge/intel/i82801gx/usb_ehci.c \
$(src)/southbridge/intel/i82801gx/usb.c \
$(src)/southbridge/intel/i82801gx/watchdog.c
# $(src)/southbridge/intel/i82801gx/libsmbus.c \
STAGE0_CHIPSET_SRC += \
$(src)/southbridge/intel/i82801gx/stage1_smbus.c \

2
southbridge/intel/i82801gx/ac97.c
View file

@ -38,7 +38,7 @@ static void ac97_modem_init(struct device *dev)
{
// XXX init modem?
}
void i82801gx_enable(struct device * dev);
/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
/* Note: 82801GU (ICH7-U) doesn't have AC97 audio. */
struct device_operations ac97audio = {

5
southbridge/intel/i82801gx/lpc.c
View file

@ -25,6 +25,7 @@
#include <msr.h>
#include <legacy.h>
#include <device/pci_ids.h>
#include <io.h>
#include <statictree.h>
#include <config.h>
#include "i82801gx.h"
@ -144,7 +145,7 @@ static void i82801gx_power_options(struct device * dev)
reg8 |= (3 << 4); /* avoid #S4 assertions */
pci_write_config8(dev, GEN_PMCON_3, reg8);
printk_info("Set power %s after power failure.\n", pwr_on ? "on" : "off");
printk(BIOS_INFO, "Set power %s after power failure.\n", pwr_on ? "on" : "off");
/* Set up NMI on errors. */
reg8 = inb(0x61);
@ -329,7 +330,7 @@ static void set_subsystem(struct device * dev, unsigned vendor, unsigned device)
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
};
void i82801gx_enable(struct device * dev);
/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
struct device_operations ich7_ich7r_ich7dh_lpc = {
.id = {.type = DEVICE_ID_PCI,

2
southbridge/intel/i82801gx/nic.c
View file

@ -38,7 +38,7 @@ static void nic_init(struct device *dev)
/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
/* Note: 82801GU (ICH7-U) doesn't have a NIC. */
/* PCI ID loaded from EEPROM. If EEPROM is 0, 0x27dc is used. */
struct device_operations = {
struct device_operations i82801gx_nic= {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x27dc}}},

10
southbridge/intel/i82801gx/pci.c
View file

@ -61,7 +61,7 @@ static void ich_pci_dev_enable_resources(struct device *dev)
/* Set the subsystem vendor and device id for mainboard devices */
ops = ops_pci(dev);
if (dev->on_mainboard && ops && ops->set_subsystem) {
printk_debug("%s subsystem <- %02x/%02x\n",
printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
dev_path(dev),
MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
@ -77,7 +77,7 @@ static void ich_pci_dev_enable_resources(struct device *dev)
*/
command = pci_read_config16(dev, PCI_COMMAND);
command |= dev->command;
printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
pci_write_config16(dev, PCI_COMMAND, command);
#endif
}
@ -93,7 +93,7 @@ static void ich_pci_bus_enable_resources(struct device *dev)
ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
ctrl |= dev->link[0].bridge_ctrl;
ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
/* This is the reason we need our own pci_bus_enable_resources */
@ -102,7 +102,7 @@ static void ich_pci_bus_enable_resources(struct device *dev)
enable_childrens_resources(dev);
}
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void set_subsystem(struct device * dev, u16 vendor, u16 device)
{
#if 0
/* Currently disabled because it causes a "BAR 9" memory resource
@ -110,7 +110,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
*/
u32 pci_id;
printk_debug("Setting PCI bridge subsystem ID\n");
printk(BIOS_DEBUG, "Setting PCI bridge subsystem ID\n");
pci_id = pci_read_config32(dev, 0);
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_id );
#endif

2
southbridge/intel/i82801gx/pcie.c
View file

@ -67,7 +67,7 @@ static void pci_init(struct device *dev)
printk(BIOS_DEBUG, " PMLU32 = 0x%08x\n", reg32);
}
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void set_subsystem(struct device * dev, u16 vendor, u16 device)
{
u32 pci_id;

13
southbridge/intel/i82801gx/sata.c
View file

@ -29,7 +29,7 @@
#include <config.h>
#include "i82801gx.h"
typedef struct southbridge_intel_i82801gx_config config_t;
typedef struct southbridge_intel_i82801gx_sata_config config_t;
static void sata_init(struct device *dev)
{
@ -139,16 +139,7 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0xa4, reg32);
pci_write_config8(dev, 0xa0, 0x00);
}
static struct device_operations sata_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = ,
.init = ,
.scan_bus = 0,
.enable = i82801gx_enable,
};
void i82801gx_enable(struct device * dev);
/* Desktop Non-AHCI and Non-RAID Mode */
/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
struct device_operations i82801gx_sata_normal_driver = {

5
southbridge/intel/i82801gx/sata.dts
View file

@ -20,4 +20,9 @@
{
device_operations = "i82801gx_sata_normal_driver";
ide_legacy_combined = "0";
ide_enable_primary = "0";
ide_enable_secondary = "0";
sata_ahci = "0";
};

6
southbridge/intel/i82801gx/smbus.c
View file

@ -25,12 +25,13 @@
#include <msr.h>
#include <legacy.h>
#include <device/pci_ids.h>
#include <device/smbus.h>
#include <statictree.h>
#include <config.h>
#include "i82801gx.h"
#include "i82801_smbus.h"
#include "i82801gx_smbus.h"
int smbus_read_byte(struct bus *bus, device_t dev, u8 address)
int smbus_read_byte(struct bus *bus, struct device * dev, u8 address)
{
u16 device;
struct resource *res;
@ -44,6 +45,7 @@ int smbus_read_byte(struct bus *bus, device_t dev, u8 address)
static struct smbus_bus_operations lops_smbus_bus = {
.read_byte = smbus_read_byte,
};
void i82801gx_enable(struct device * dev)
/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
struct device_operations i82801gx_smbus = {