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Working fake SPD for DBE61C
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@987 f3766cd6-281f-0410-b1cd-43a5c92072e9
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1 changed files with 27 additions and 18 deletions
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@ -38,31 +38,39 @@
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#define DIMM0 ((u8) 0xA0)
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#define DIMM1 ((u8) 0xA2)
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/* The part is a Hynix hy5du121622ctp-d43.
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*
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* HY 5D U 12 16 2 2 C <blank> T <blank> P D43
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* Hynix
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* DDR SDRAM (5D)
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* VDD 2.5 VDDQ 2.5 (U)
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* 512M 8K REFRESH (12)
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* x16 (16)
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* 4banks (2)
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* SSTL_2 (2)
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* 4th GEN die (C)
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* Normal Power Consumption (<blank> )
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* TSOP (T)
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* Single Die (<blank>)
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* Lead Free (P)
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* DDR400 3-3-3 (D43)
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*/
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struct spd_entry {
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u8 address;
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u8 data;
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};
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/* Save space by using a short list of SPD values used by Geode LX Memory init */
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/* Fake SPD for DBE61C - 256MB. Same memory chip, and therefore same SPD entries, as for DBE62. */
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/* Micron MT46V32M16 */
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static const struct spd_entry spd_table[] = {
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{SPD_MEMORY_TYPE, 7},
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{SPD_NUM_ROWS, 13},
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{SPD_tRFC, 0x4b},
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{SPD_ACCEPTABLE_CAS_LATENCIES, 0x10},
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{SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x40},
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{SPD_tRAS, 0x2d},
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{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x7}, /*0x <= 7},*/
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{SPD_MIN_RAS_TO_CAS_DELAY, 0x58},
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{SPD_tRRD, 0x3c},
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{SPD_tRP, 0x58},
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{SPD_PRIMARY_SDRAM_WIDTH, 8},
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{SPD_NUM_BANKS_PER_SDRAM, 0x4},
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{SPD_NUM_COLUMNS, 0xa}, /* 8kB */
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{SPD_NUM_DIMM_BANKS, 0x1},
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{SPD_REFRESH, 0x82},
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{SPD_SDRAM_CYCLE_TIME_2ND, 0x0},
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{SPD_SDRAM_CYCLE_TIME_3RD, 0x0},
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{SPD_tRCD, 15},
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};
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#if 0
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/* Fake SPD for DBE61A - 128MB. Not working yet */
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/* Micron MT46V16M16 */
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static const struct spd_entry spd_table_dbe61a[] = {
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{SPD_ACCEPTABLE_CAS_LATENCIES, 0x10},
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{SPD_BANK_DENSITY, 0x40},
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{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff},
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@ -83,6 +91,7 @@ static const struct spd_entry spd_table[] = {
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{SPD_tRP, 15},
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{SPD_tRRD, 10},
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};
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#endif
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/**
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* Given an SMBUS device, and an address in that device, return the value of SPD
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