Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

I'm committing often as I don't want people to run over each other (and I am waiting on BlueGene to schedule me

Browse source 
and keep getting called away ... waiting for 1024 procs takes patience!)

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1008 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-11-12 22:43:50 +00:00
parent 0a43cd94c1
commit f37c28c24b
6 changed files with 14 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
arch/x86/intel/core2/stage0.S
View file

@ -18,12 +18,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE
#define post_code(x) intel_chip_post_macro(x)
#define ASSEMBLY
#define CACHE_AS_RAM_SIZE CONFIG_CARSIZE
#define CACHE_AS_RAM_BASE CONFIG_CARBASE
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <mtrr.h>
#include <macros.h>
@ -67,7 +66,7 @@ __protected_stage0:
cache_as_ram:
#if USE_FALLBACK_IMAGE == 1
post_code(0x20)
port80_post(0x20)
/* Send INIT IPI to all excluding ourself */
movl $0x000C4500, %eax
@ -164,11 +163,11 @@ clear_mtrrs:
movl %esp, %ebp
pushl %eax
post_code(0x23)
port80_post(0x23)
call stage1_phase1
post_code(0x2f)
port80_post(0x2f)
error:
hlt
jmp error

2
mainboard/kontron/986lcd-m/Makefile
View file

@ -26,7 +26,7 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/northbridge/intel/i945/raminit.c \
$(src)/northbridge/intel/i945/raminit.c \
STAGE2_MAINBOARD_SRC =

7
northbridge/intel/i945/Makefile
View file

@ -21,11 +21,6 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y)
STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i945/get_sblk_pci1234.c \
$(src)/northbridge/intel/i945/common.c \
$(src)/northbridge/intel/i945/cpu.c \
$(src)/northbridge/intel/i945/domain.c \
$(src)/northbridge/intel/i945/pci.c \
$(src)/northbridge/intel/i945/util.c
STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i945/northbridge.c \
endif

3
northbridge/intel/i945/northbridge.c
View file

@ -259,10 +259,11 @@ static void cpu_bus_noop(struct device * dev)
{
}
#warning get a number of the 945 mc
struct device_operations i945_mc_ops = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_INTEL,
.device = anu,ber}}},
.device = 0x1233}}},
.constructor = default_device_constructor,
.phase4_read_resources = cpu_bus_noop,
.phase4_set_resources = cpu_bus_noop,

4
southbridge/intel/i82801gx/Makefile
View file

@ -32,13 +32,13 @@ STAGE2_CHIPSET_SRC += \
$(src)/southbridge/intel/i82801gx/pcie.c \
$(src)/southbridge/intel/i82801gx/sata.c \
$(src)/southbridge/intel/i82801gx/smbus.c \
$(src)/southbridge/intel/i82801gx/libsmbus.c \
$(src)/southbridge/intel/i82801gx/usb_ehci.c \
$(src)/southbridge/intel/i82801gx/usb.c \
$(src)/southbridge/intel/i82801gx/watchdog.c
# $(src)/southbridge/intel/i82801gx/libsmbus.c \
STAGE0_CHIPSET_SRC += \
$(src)/southbridge/intel/i82801gx/stage1_smbus.c \
$(src)/southbridge/intel/i82801gx/libsmbus.c \
# $(src)/southbridge/intel/i82801gx/libsmbus.c \
endif

1
southbridge/intel/i82801gx/usb.c
View file

@ -46,6 +46,7 @@ static void usb_init(struct device *dev)
printk(BIOS_DEBUG, "done.\n");
}
void i82801gx_enable(struct device * dev);
/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
struct device_operations i82801gb_usb1 = {