Modify chipset_flash_setup to support enabling NAND flash on other locations
than CS0, by making enable_ide_nand_flash have a non-boolean meaning where zero
means no NAND (IDE), and 1 through 4 gives the one-based chip select array
location (so 1 means CS0, 2 means CS1, 3 means CS2 and 4 means CS3, as chip
select notation is zero-based).
This loses the code for supporting more than one NAND chip select or different
ones than FLASH_MEM_4K, but these couldn't be supported before anyway, because
that is board specific, but the supporting structure was a static const struct
in generic southbridge specific code.
This support should be instead implemented via the device tree dts files.
Enables NAND on ArtecGroup DBE61 and DBE62 on CS1, as that's where it is.
The end result is that these mainboards can now boot off of NAND with FILO
without local modifications to the previously existing southbridge specific
static const struct that had no chance of being upstreamed as it would break
all other CS5536 NAND boards that have it on CS0.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@985 f3766cd6-281f-0410-b1cd-43a5c92072e9
table get rebuilt unconditionally due to slightly incorrect
dependencies.
That's wasteful and may hide other dependency bugs.
Fix the lar, lzma, nrv2b and option table dependencies.
This trims down recompilation time a lot. The only remaining stuff being
rebuilt is:
~/corebootv3-better_dependencies> make
CP build/config.h
GEN build/build.h
LAR build/coreboot.rom
PAYLOAD none (as specified by user)
CP build/bios.bin
DONE
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@984 f3766cd6-281f-0410-b1cd-43a5c92072e9
The largest changes are to get_pci_bridge_ops, and related changes to make it
compile and use correct declarations.
While I was doing that I moved the checks for CONFIG_<BUS>_PLUGIN_SUPPORT to
the Makefile.
The only functional difference is a possible NULL dereference in a debug
statement.
I also added a few more consts, now that my other patch is in.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@983 f3766cd6-281f-0410-b1cd-43a5c92072e9
It also changes %p debug statements in various places. I think they get in
the way of diffs when you have log files to compare. I don't want to see the
allocation differences most of the time. I turned most of them into NULL
checks. If they were supposed to be "Where are we in device allocation?"
checks, we could make them into that too.
It's a work-in-progress. Comments welcome.
I think most of the changes are self explanatory, but this one might not be:
If you are reading all the BARs from a device, and you come to a 64-bit BAR.
No matter why you skip it, you should skip it as a 64-bit BAR, and not try to
read the upper half as the next 32-bit BAR.
Because of that, set the 64-bit flag IORESOURCE_PCI64 early, and don't clear
it on return.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@980 f3766cd6-281f-0410-b1cd-43a5c92072e9
workarounds are better than instant reboots, mangle the code so that it
only switches stacks and flushes the cache.
There are two genuine fix in there as well:
We have to switch %esp before CAR is disabled. That way, the stack is
always valid.
And one of the nastier bugs easily happening in C: We had a pointer to a
const struct, but we wanted a const pointer to a struct. This kills the
(correct) warning about that code.
Many thanks to Corey for testing countless iterations of that code.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested and
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@978 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@976 f3766cd6-281f-0410-b1cd-43a5c92072e9
Make cmos.layout work with incomprehensible tool -- just turn off checksums.
Add static.c to list of files covered by kscope
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@975 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@974 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@973 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@972 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@971 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmai.com>
Acked-by: Ronald G. Minnich <rminnich@gmai.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@970 f3766cd6-281f-0410-b1cd-43a5c92072e9
mainboard.h -- we need a better way to do this. We should not have to specify address bits in
this way. But it is not as easy a problem as it seems.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@969 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@968 f3766cd6-281f-0410-b1cd-43a5c92072e9
Does not yet build
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@967 f3766cd6-281f-0410-b1cd-43a5c92072e9
alue. There
is a known bug in v2/v3 wherein a BAR that is set is ignored. This change will c
ome in very
slowly as it is a bit tricky to get right as we redesign the dev code.
Also make the vm86 stuff use the SRC instead of OBJ names so we can see it in ks
cope.
Finally, beginnings of documentation changes, not finished yet.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@965 f3766cd6-281f-0410-b1cd-43a5c92072e9
1. moves the run_bios function down so it can call setup_realmode_idt
2. adds the __attribute__((regnum(0))) to biosint because it is called from assembly
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@964 f3766cd6-281f-0410-b1cd-43a5c92072e9
dev_phase4 will call compute_allocate. This is an early pass at
making the device tree code a little more readable. We have done a
pass on the stage2 code and are comfortable with phases 1-3 and 5-6;
phase 4 is the phase that is really tough to follow. We are working
on cleaning that up today.
This change tested and working on dbe62.
We are well aware that as more complex targets appear this code
may break on them. At the same time, we are determined to untangle the
thicket of code in phase 4, since this code has been a source of
confusion for several years now.
There used to be a recursion: compute_allocate_resource would ALWAYS
call read_resources, which would in turn call compute_allocate_resource.
We are attempting to resolve this in a clearer manner.
boots to linux on dbe62
boots to etherboot on qemu
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@963 f3766cd6-281f-0410-b1cd-43a5c92072e9
Most substantive change is getting rid of 'initialized', which was only
ever needed in v2 due to an implementation mistake.
With Uwe's comments taken into account,
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@961 f3766cd6-281f-0410-b1cd-43a5c92072e9
cleans up the NULL pointer protection.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@960 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@955 f3766cd6-281f-0410-b1cd-43a5c92072e9
cleanups/fixes.
Fixup device tree code. Add/change methods as needed.
This should help serengeti.
Signed-off-by: Ronald G. Minnich<rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@954 f3766cd6-281f-0410-b1cd-43a5c92072e9
Self-acked, as this was acked/committed in v2 already (r3680).
Build-tested with the AMD dbm690t target.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@948 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@947 f3766cd6-281f-0410-b1cd-43a5c92072e9
CAR disabling operation. Untested, but it should work.
Please note that the code is incomplete, but that should at least not
affect stage2.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@945 f3766cd6-281f-0410-b1cd-43a5c92072e9
1. fix if->in in comments
2. change width of output for different types
3. make all masks 0x so that it's easy to tell a mask
It also changes the invocations to do function 1 instead of 0.
I think we should consider a name that makes it clear that this is only good
for AMD K8+ processors function 1. We might need a similar utility for other
functions later.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@943 f3766cd6-281f-0410-b1cd-43a5c92072e9
I am totally convinced these are right. I am going on travel for a week
and want these in your hands.
Carl-Daniel as acked these, but for lack of time to get firefox going
right now,
Current serengeti output
DRAM(40)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(48)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(50)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(58)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(60)00000000-00ffffff, ->(4), , , No interleave, 0
DRAM(68)00000000-00ffffff, ->(0), R, W, 8 nodes, 0
DRAM(70)00000000-00ffffff, ->(0), , , No interleave, 0
DRAM(78)00000000-00ffffff, ->(0), , , No interleave, 0
MMIO(80)01a00000-1100ffff, ->(0,2), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(88)75060000-0000ffff, ->(2,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(90)51040000-3f00ffff, ->(0,0), , , CPU disable 1, Lock 0, Non
posted 0
MMIO(98)00000000-0000ffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non
posted 0
MMIO(a0)01c00000-1100ffff, ->(0,1), , , CPU disable 0, Lock 0, Non
posted 1
MMIO(a8)75000000-0000ffff, ->(2,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(b0)51040000-0000ffff, ->(0,0), , , CPU disable 1, Lock 0, Non
posted 0
MMIO(b8)00000000-0000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
PCIIO(c0)00001010-00003110, ->(0,1), , ,VGA 0 ISA 0
PCIIO(c8)00000750-00000000, ->(2,0), , ,VGA 0 ISA 1
PCIIO(d0)00002510-00000000, ->(0,0), , ,VGA 1 ISA 0
PCIIO(d8)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0
CONFIG(e0)00000000-00000000 ->(0,0), CE 0
CONFIG(e4)00000000-00000000 ->(0,0), CE 0
CONFIG(e8)00000000-00000000 ->(0,0), CE 0
CONFIG(ec)00000000-00000000 ->(0,0), CE 0
Either the DRAM output is wrong or there is a real problem with our
DRAM programming.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@941 f3766cd6-281f-0410-b1cd-43a5c92072e9
expansion ROMs are active.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@940 f3766cd6-281f-0410-b1cd-43a5c92072e9
with testing of real serengeti
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@939 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@938 f3766cd6-281f-0410-b1cd-43a5c92072e9
the reserved regions substracted from them. This patch introduces a check
to weed them out, splitting when necessary
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@937 f3766cd6-281f-0410-b1cd-43a5c92072e9
arch_write_tables(), before a number of routines that write/reserve
stuff are executed (in my test this only affects the 0x0-0x500 region
but I notice there's other stuff too).
Attached patch moves it down, solving the problem. Because stage1 can no
longer assume the MBI is at 0xf0000, I had to add a return path for stage2
to give it a pointer, using its exit status value.
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@936 f3766cd6-281f-0410-b1cd-43a5c92072e9
