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https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
This patch fixes whitespace so that my next patch is easier to read.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> Thanks, Myles git-svn-id: svn://coreboot.org/repository/coreboot-v3@952 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson
parent
9b90a6f22b
commit
7e654ac7a0
2 changed files with 101 additions and 99 deletions
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@ -76,6 +76,7 @@ void debug_fx_devs(void)
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}
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}
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#endif
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void get_fx_devs(void)
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{
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int i;
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@ -123,48 +124,48 @@ struct hw_mem_hole_info get_hw_mem_hole_info(void)
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struct hw_mem_hole_info mem_hole;
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int i;
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mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
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mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
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mem_hole.node_id = -1;
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for (i = 0; i < 8; i++) {
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u32 base;
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u32 hole;
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base = f1_read_config32(0x40 + (i << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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}
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hole = pci_read_config32(__f1_dev[i], 0xf0);
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if(hole & 1) { // we find the hole
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mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
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mem_hole.node_id = i; // record the node No with hole
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break; // only one hole
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for (i = 0; i < 8; i++) {
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u32 base;
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u32 hole;
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base = f1_read_config32(0x40 + (i << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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}
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}
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//We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
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if(mem_hole.node_id==-1) {
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u32 limitk_pri = 0;
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for(i=0; i<8; i++) {
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u32 base, limit;
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unsigned base_k, limit_k;
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base = f1_read_config32(0x40 + (i << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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}
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hole = pci_read_config32(__f1_dev[i], 0xf0);
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if(hole & 1) { // we find the hole
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mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
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mem_hole.node_id = i; // record the node No with hole
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break; // only one hole
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}
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}
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base_k = (base & 0xffff0000) >> 2;
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if(limitk_pri != base_k) { // we find the hole
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mem_hole.hole_startk = limitk_pri;
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mem_hole.node_id = i;
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break; //only one hole
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//We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
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if(mem_hole.node_id==-1) {
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u32 limitk_pri = 0;
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for(i=0; i<8; i++) {
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u32 base, limit;
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unsigned base_k, limit_k;
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base = f1_read_config32(0x40 + (i << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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}
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limit = f1_read_config32(0x44 + (i << 3));
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limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
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limitk_pri = limit_k;
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}
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}
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base_k = (base & 0xffff0000) >> 2;
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if(limitk_pri != base_k) { // we find the hole
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mem_hole.hole_startk = limitk_pri;
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mem_hole.node_id = i;
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break; //only one hole
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}
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limit = f1_read_config32(0x44 + (i << 3));
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limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
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limitk_pri = limit_k;
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}
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}
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return mem_hole;
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@ -172,35 +173,35 @@ struct hw_mem_hole_info get_hw_mem_hole_info(void)
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void disable_hoist_memory(unsigned long hole_startk, int i)
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{
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int ii;
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struct device * dev;
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u32 base, limit;
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u32 hoist;
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int ii;
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struct device * dev;
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u32 base, limit;
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u32 hoist;
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u32 hole_sizek;
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//1. find which node has hole
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//2. change limit in that node.
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//3. change base and limit in later node
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//4. clear that node f0
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//1. find which node has hole
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//2. change limit in that node.
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//3. change base and limit in later node
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//4. clear that node f0
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//if there is not mem hole enabled, we need to change it's base instead
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hole_sizek = (4*1024*1024) - hole_startk;
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for(ii=7;ii>i;ii--) {
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for(ii=7;ii>i;ii--) {
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base = f1_read_config32(0x40 + (ii << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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}
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base = f1_read_config32(0x40 + (ii << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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}
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limit = f1_read_config32(0x44 + (ii << 3));
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f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
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f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
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}
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limit = f1_read_config32(0x44 + (i << 3));
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f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
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dev = __f1_dev[i];
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f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
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f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
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}
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limit = f1_read_config32(0x44 + (i << 3));
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f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
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dev = __f1_dev[i];
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hoist = pci_read_config32(dev, 0xf0);
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if(hoist & 1) {
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pci_write_config32(dev, 0xf0, 0);
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@ -214,30 +215,30 @@ void disable_hoist_memory(unsigned long hole_startk, int i)
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u32 hoist_memory(unsigned long hole_startk, int i)
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{
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int ii;
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u32 carry_over;
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struct device * dev;
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u32 base, limit;
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u32 basek;
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u32 hoist;
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int ii;
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u32 carry_over;
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struct device * dev;
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u32 base, limit;
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u32 basek;
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u32 hoist;
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carry_over = (4*1024*1024) - hole_startk;
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carry_over = (4*1024*1024) - hole_startk;
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for(ii=7;ii>i;ii--) {
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for(ii=7;ii>i;ii--) {
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base = f1_read_config32(0x40 + (ii << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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}
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base = f1_read_config32(0x40 + (ii << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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}
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limit = f1_read_config32(0x44 + (ii << 3));
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f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
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f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
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}
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limit = f1_read_config32(0x44 + (i << 3));
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f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
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dev = __f1_dev[i];
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base = pci_read_config32(dev, 0x40 + (i << 3));
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basek = (base & 0xffff0000) >> 2;
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f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
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f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
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}
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limit = f1_read_config32(0x44 + (i << 3));
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f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
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dev = __f1_dev[i];
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base = pci_read_config32(dev, 0x40 + (i << 3));
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basek = (base & 0xffff0000) >> 2;
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if(basek == hole_startk) {
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//don't need set memhole here, because hole off set will be 0, overflow
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//so need to change base reg instead, new basek will be 4*1024*1024
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@ -247,17 +248,17 @@ u32 hoist_memory(unsigned long hole_startk, int i)
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}
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else
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{
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hoist = /* hole start address */
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((hole_startk << 10) & 0xff000000) +
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/* hole address to memory controller address */
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(((basek + carry_over) >> 6) & 0x0000ff00) +
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/* enable */
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1;
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hoist = /* hole start address */
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((hole_startk << 10) & 0xff000000) +
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/* hole address to memory controller address */
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(((basek + carry_over) >> 6) & 0x0000ff00) +
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/* enable */
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1;
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pci_write_config32(dev, 0xf0, hoist);
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pci_write_config32(dev, 0xf0, hoist);
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}
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return carry_over;
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return carry_over;
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}
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#endif
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@ -126,18 +126,18 @@ static void k8_pci_domain_read_resources(struct device * dev)
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}
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}
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#ifndef CONFIG_PCI_64BIT_PREF_MEM
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/* Initialize the system wide io space constraints */
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/* Initialize the system-wide io space constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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resource->base = 0x400;
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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/* Initialize the system wide memory resources constraints */
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/* Initialize the system-wide memory resource constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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resource->limit = 0xfcffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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#else
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/* Initialize the system wide io space constraints */
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/* Initialize the system-wide io space constraints */
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resource = new_resource(dev, 0);
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resource->base = 0x400;
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resource->limit = 0xffffUL;
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@ -145,7 +145,7 @@ static void k8_pci_domain_read_resources(struct device * dev)
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compute_allocate_resource(&dev->link[0], resource,
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IORESOURCE_IO, IORESOURCE_IO);
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/* Initialize the system wide prefetchable memory resources constraints */
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/* Initialize the system-wide prefetchable memory resource constraints */
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resource = new_resource(dev, 1);
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resource->limit = 0xfcffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
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@ -153,7 +153,7 @@ static void k8_pci_domain_read_resources(struct device * dev)
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IORESOURCE_MEM | IORESOURCE_PREFETCH,
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IORESOURCE_MEM | IORESOURCE_PREFETCH);
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/* Initialize the system wide memory resources constraints */
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/* Initialize the system-wide memory resource constraints */
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resource = new_resource(dev, 2);
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resource->limit = 0xfcffffffffULL;
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resource->flags = IORESOURCE_MEM;
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@ -197,10 +197,10 @@ static void k8_pci_domain_set_resources(struct device * dev)
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mem2 = find_resource(dev, 2);
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#if 1
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printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem1->base, mem1->limit, mem1->size, mem1->align);
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printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem2->base, mem2->limit, mem2->size, mem2->align);
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printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem1->base, mem1->limit, mem1->size, mem1->align);
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printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem2->base, mem2->limit, mem2->size, mem2->align);
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#endif
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/* See if both resources have roughly the same limits */
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@ -227,10 +227,10 @@ static void k8_pci_domain_set_resources(struct device * dev)
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}
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#if 1
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printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem1->base, mem1->limit, mem1->size, mem1->align);
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printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem2->base, mem2->limit, mem2->size, mem2->align);
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printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem1->base, mem1->limit, mem1->size, mem1->align);
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printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem2->base, mem2->limit, mem2->size, mem2->align);
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#endif
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last = &dev->resource[dev->resources];
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@ -264,10 +264,11 @@ static void k8_pci_domain_set_resources(struct device * dev)
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#endif
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#if CONFIG_HW_MEM_HOLE_SIZEK != 0
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/* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
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* if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
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* otherwise We reset the hole to the mmio_basek
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*/
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/* If the hw mem hole is already set in raminit stage, here we will
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* compare mmio_basek and hole_basek. If mmio_basek is bigger than
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* hole_basek, we use hole_basek as mmio_basek and we don't need
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* to reset hole. Otherwise, we reset the hole to the mmio_basek.
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*/
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mem_hole = get_hw_mem_hole_info();
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