mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Simplify the PM/PM2 related functions and make them more readable.
Self-acked, as this was acked/committed in v2 already (r3680). Build-tested with the AMD dbm690t target. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@948 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
parent
e0ab3a5564
commit
2174dd2c78
3 changed files with 19 additions and 15 deletions
|
@ -62,8 +62,8 @@ void set_sm_enable_bits(struct device * sm_dev, u32 reg_pos, u32 mask, u32 val)
|
|||
}
|
||||
}
|
||||
|
||||
void pmio_write_index(unsigned long port_base, u8 reg, u8 value);
|
||||
u8 pmio_read_index(unsigned long port_base, u8 reg);
|
||||
void pmio_write_index(u16 port_base, u8 reg, u8 value);
|
||||
u8 pmio_read_index(u16 port_base, u8 reg);
|
||||
u8 pm_ioread(u8 reg);
|
||||
void pm_iowrite(u8 reg, u8 value);
|
||||
void pm2_iowrite(u8 reg, u8 value);
|
||||
|
|
|
@ -22,6 +22,12 @@
|
|||
|
||||
#include <device/pci_ids.h>
|
||||
|
||||
/* Power management index/data registers */
|
||||
#define PM_INDEX 0xcd6
|
||||
#define PM_DATA 0xcd7
|
||||
#define PM2_INDEX 0xcd0
|
||||
#define PM2_DATA 0xcd1
|
||||
|
||||
void pm_iowrite(u8 reg, u8 value);
|
||||
u8 pm_ioread(u8 reg);
|
||||
void pm2_iowrite(u8 reg, u8 value);
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <lib.h>
|
||||
#include <console.h>
|
||||
|
@ -29,15 +30,15 @@
|
|||
#include <io.h>
|
||||
#include <cpu.h>
|
||||
#include "sb600_smbus.h"
|
||||
#include "sb600.h"
|
||||
|
||||
|
||||
void pmio_write_index(unsigned long port_base, u8 reg, u8 value)
|
||||
void pmio_write_index(u16 port_base, u8 reg, u8 value)
|
||||
{
|
||||
outb(reg, port_base);
|
||||
outb(value, port_base + 1);
|
||||
}
|
||||
|
||||
u8 pmio_read_index(unsigned long port_base, u8 reg)
|
||||
u8 pmio_read_index(u16 port_base, u8 reg)
|
||||
{
|
||||
outb(reg, port_base);
|
||||
return inb(port_base + 1);
|
||||
|
@ -45,27 +46,25 @@ u8 pmio_read_index(unsigned long port_base, u8 reg)
|
|||
|
||||
void pm_iowrite(u8 reg, u8 value)
|
||||
{
|
||||
unsigned long port_base = 0xcd6;
|
||||
pmio_write_index(port_base, reg, value);
|
||||
pmio_write_index(PM_INDEX, reg, value);
|
||||
}
|
||||
|
||||
u8 pm_ioread(u8 reg)
|
||||
{
|
||||
unsigned long port_base = 0xcd6;
|
||||
return pmio_read_index(port_base, reg);
|
||||
return pmio_read_index(PM_INDEX, reg);
|
||||
}
|
||||
|
||||
void pm2_iowrite(u8 reg, u8 value)
|
||||
{
|
||||
unsigned long port_base = 0xcd0;
|
||||
pmio_write_index(port_base, reg, value);
|
||||
pmio_write_index(PM2_INDEX, reg, value);
|
||||
}
|
||||
|
||||
u8 pm2_ioread(u8 reg)
|
||||
{
|
||||
unsigned long port_base = 0xcd0;
|
||||
return pmio_read_index(port_base, reg);
|
||||
}/* Get SB ASIC Revision.*/
|
||||
return pmio_read_index(PM2_INDEX, reg);
|
||||
}
|
||||
|
||||
/* Get SB ASIC Revision.*/
|
||||
static u8 get_sb600_revision(void)
|
||||
{
|
||||
u32 dev;
|
||||
|
@ -75,7 +74,6 @@ static u8 get_sb600_revision(void)
|
|||
return pci_conf1_read_config8(dev, 0x08);
|
||||
}
|
||||
|
||||
|
||||
/***************************************
|
||||
* Legacy devices are mapped to LPC space.
|
||||
* serial port 0
|
||||
|
|
Loading…
Add table
Reference in a new issue