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Add functions to print routes.

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I am totally convinced these are right. I am going on travel for a week 
and want these in your hands. 

Carl-Daniel as acked these, but for lack of time to get firefox going 
right now, 

Current serengeti output
DRAM(40)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(48)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(50)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(58)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(60)00000000-00ffffff, ->(4), , , No interleave, 0
DRAM(68)00000000-00ffffff, ->(0), R, W, 8 nodes, 0
DRAM(70)00000000-00ffffff, ->(0), , , No interleave, 0
DRAM(78)00000000-00ffffff, ->(0), , , No interleave, 0
MMIO(80)01a00000-1100ffff, ->(0,2), , , CPU disable 0, Lock 0, Non 
posted 0
MMIO(88)75060000-0000ffff, ->(2,0), , , CPU disable 0, Lock 0, Non 
posted 0
MMIO(90)51040000-3f00ffff, ->(0,0), , , CPU disable 1, Lock 0, Non 
posted 0
MMIO(98)00000000-0000ffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non 
posted 0
MMIO(a0)01c00000-1100ffff, ->(0,1), , , CPU disable 0, Lock 0, Non 
posted 1
MMIO(a8)75000000-0000ffff, ->(2,0), , , CPU disable 0, Lock 0, Non 
posted 0
MMIO(b0)51040000-0000ffff, ->(0,0), , , CPU disable 1, Lock 0, Non 
posted 0
MMIO(b8)00000000-0000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non 
posted 0
PCIIO(c0)00001010-00003110, ->(0,1), , ,VGA 0 ISA 0
PCIIO(c8)00000750-00000000, ->(2,0), , ,VGA 0 ISA 1
PCIIO(d0)00002510-00000000, ->(0,0), , ,VGA 1 ISA 0
PCIIO(d8)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0
CONFIG(e0)00000000-00000000 ->(0,0),  CE 0
CONFIG(e4)00000000-00000000 ->(0,0),  CE 0
CONFIG(e8)00000000-00000000 ->(0,0),  CE 0
CONFIG(ec)00000000-00000000 ->(0,0),  CE 0

Either the DRAM output is wrong or there is a real problem with our 
DRAM programming. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@941 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-10-21 03:20:05 +00:00
parent ff5c45493d
commit 979bdb5ed0
7 changed files with 310 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
include/arch/x86/amd/k8/k8.h
View file

@ -131,6 +131,18 @@
#define HTIC_INIT_Detect (1<<6)
/* Function 1 */
/* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at
* 0x78, 0xb8, and 0xd8
*/
#define DRAM_ROUTE_START 0x40
#define DRAM_ROUTE_END 0x78
#define MMIO_ROUTE_START 0x80
#define MMIO_ROUTE_END 0xb8
#define PCIIO_ROUTE_START 0xc0
#define PCIIO_ROUTE_END 0xd8
#define CONFIG_ROUTE_START 0xe0
#define CONFIG_ROUTE_END 0xec
#define PCI_IO_BASE0 0xc0
#define PCI_IO_BASE1 0xc8
#define PCI_IO_BASE2 0xd0
@ -683,6 +695,10 @@ void init_fidvid_bsp(unsigned bsp_apicid);
/* k8/northbridge.c */
void sdram_initialize(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo);
/* k8 router printing */
void showallroutes(int level, u32 dev);
/* k8/reset_test.c */
void distinguish_cpu_resets(unsigned nodeid);

3
mainboard/amd/serengeti/Makefile
View file

@ -40,6 +40,7 @@ INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/k8/reset_test.c \
$(src)/northbridge/amd/k8/coherent_ht.c \
$(src)/northbridge/amd/k8/incoherent_ht.c \
$(src)/northbridge/amd/k8/util.c \
$(src)/arch/x86/pci_ops_conf1.c \
$(src)/arch/x86/stage1_mtrr.c \
$(src)/southbridge/amd/amd8111/stage1_smbus.c \
@ -49,7 +50,7 @@ INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/lib/clog2.c
STAGE2_MAINBOARD_SRC =
STAGE2_MAINBOARD_SRC = mainboard.c
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"

1
mainboard/amd/serengeti/dts
View file

@ -19,6 +19,7 @@
*/
/{
device_operations="serengeti";
mainboard_vendor = "AMD";
mainboard_name = "Serengeti";
cpus { };

3
mainboard/amd/serengeti/initram.c
View file

@ -127,6 +127,7 @@ int main(void)
void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn);
void soft_reset_x(unsigned sbbusn, unsigned sbdn);
int cpu_init_detected(unsigned int nodeid);
u32 init_detected;
static const u16 spd_addr[] = {
//first node
@ -249,6 +250,8 @@ int main(void)
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif
showallroutes(BIOS_DEBUG, PCI_BDF(0,0x18, 0));
printk(BIOS_DEBUG, "stage1 returns\n");
return 0;
}

48
mainboard/amd/serengeti/mainboard.c Normal file
View file

@ -0,0 +1,48 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <mainboard.h>
#include <config.h>
#include <types.h>
#include <lib.h>
#include <console.h>
#include <cpu.h>
#include <globalvars.h>
#include <device/device.h>
#include <device/pci.h>
#include <string.h>
#include <msr.h>
#include <io.h>
#include <amd/k8/k8.h>
#include <mc146818rtc.h>
#include <spd.h>
static void show(struct device *dev)
{
showallroutes(BIOS_DEBUG, PCI_BDF(0,0x18, 0));
}
struct device_operations serengeti = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
.device = 1}}},
.constructor = default_device_constructor,
.phase6_init = show,
};

3
northbridge/amd/k8/Makefile
View file

@ -26,6 +26,7 @@ STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/k8/get_sblk_pci1234.c \
$(src)/northbridge/amd/k8/common.c \
$(src)/northbridge/amd/k8/cpu.c \
$(src)/northbridge/amd/k8/domain.c \
$(src)/northbridge/amd/k8/pci.c
$(src)/northbridge/amd/k8/pci.c \
$(src)/northbridge/amd/k8/util.c
endif

238
northbridge/amd/k8/util.c Normal file
View file

@ -0,0 +1,238 @@
/*
* K8 northbridge utilities (dump routing registers). Designed to be called at any time.
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Vincent Legoll <vincent.legoll@gmail.com>
* Original Python code
* Convert to c (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
*/
#include <mainboard.h>
#include <console.h>
#include <string.h>
#include <mtrr.h>
#include <macros.h>
#include <spd_ddr2.h>
#include <cpu.h>
#include <msr.h>
#include <amd/k8/k8.h>
#include <amd/k8/sysconf.h>
#include <device/pci.h>
#include <pci_ops.h>
#include <mc146818rtc.h>
#include <lib.h>
#define BITS(r, shift, mask) (((r>>shift)&mask))
/**
* return "R" if the register has read-enable bit set
*/
static char *re(u32 i)
{
if (i & 1)
return "R";
else
return "";
}
/**
* return "W" if the register has read-enable bit set
*/
static char *we(u32 i)
{
if (i & 1)
return "W";
else
return "";
}
/**
* return a string containing the interleave settings.
*/
static char *ileave(u32 base)
{
switch((base >> 8) & 7) {
case 0: return "No interleave";
case 1: return "2 nodes";
case 3: return "4 nodes";
case 7: return "8 nodes";
default: return "Reserved";
}
}
/**
* Return the node number.
* For one case (config registers) these are not the right bit fields.
*/
static int node(u32 reg)
{
return BITS(reg, 0, 7);
}
/**
* Return the link number.
* For one case (config registers) these are not the right bit fields.
*/
static int link(u32 reg)
{
return BITS(reg, 4, 3);
}
/**
* Print the dram routing info for one base/limit pair.
* Show base, limit, dest node, dest link on that node, read and write enable, and
* interleave information.
* @param level printing level
* @param which Register number
* @param base Base register
* @param limit Limit register
*/
void showdram(int level, u8 which, u32 base, u32 lim)
{
printk(level, "DRAM(%02x)%08x-%08x, ->(%d), %s, %s, %s, %d\n",
which, ((base&0xfff0000)<<8),
((lim&0xffff0000<<8))+0xffffff,
node(lim), re(base), we(base),
ileave(base), (lim>>8)&3);
}
/**
* Print the config routing info for a config register.
* Show base, limit, dest node, dest link on that node, read and write enable, and
* device number compare enable
* @param level printing level
* @param which Register number
* @param reg config register
*/
void showconfig(int level, u8 which, u32 reg)
{
/* don't use node() and link() here */
printk(level, "CONFIG(%02x)%08x-%08x ->(%d,%d),%s %s CE %d\n",
which, BITS(reg, 24, 0xff), BITS(reg, 16, 0xff),
BITS(reg, 4, 7), BITS(reg, 8, 3),
re(reg), we(reg), BITS(reg, 0, 4));
}
/**
* Print the pciio routing info for one base/limit pair.
* Show base, limit, dest node, dest link on that node, read and write enable, and
* VGA and ISA Enable.
* @param level printing level
* @param which Register number
* @param base Base register
* @param limit Limit register
*/
void showpciio(int level, u8 which, u32 base, u32 lim)
{
printk(level, "PCIIO(%02x)%08x-%08x, ->(%d,%d), %s, %s,VGA %d ISA %d\n",
which, BITS(base, 12, 0x3fff), BITS(lim, 12, 0x3fff),
node(lim), link(lim),
re(base), we(base),
BITS(base, 4, 1), BITS(base, 5, 1));
}
/**
* Print the pciio routing info for one base/limit pair.
* Show base, limit, dest node, dest link on that node, read and write enable, and
* CPU Disable, Lock, and Non-posted.
* @param level printing level
* @param which Register number
* @param base Base register
* @param limit Limit register
*/
void showmmio(int level, u8 which, u32 base, u32 lim)
{
printk(level, "MMIO(%02x)%08x-%08x, ->(%d,%d), %s, %s, CPU disable %d, Lock %d, Non posted %d\n",
which, BITS(base, 0, 0xffffff00)<<8,
(BITS(lim, 0, 0xffffff00)<<8)+0xffff,
node(lim), link(lim), re(base), we(base),
BITS(base, 4, 1),
BITS(base, 7, 1), BITS(lim, 7, 1));
}
/**
* Show all dram routing registers. This function is callable at any time.
* @param level The debug level
* @param dev 32-bit number if the standard bus/dev/fn format which is used raw config space
*/
void showalldram(int level, u32 dev)
{
u8 reg;
for(reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) {
u32 base = pci_conf1_read_config32(dev, reg);
u32 lim = pci_conf1_read_config32(dev,reg+4);
showdram(level, reg, base, lim);
}
}
/**
* Show all mmio routing registers. This function is callable at any time.
* @param level The debug level
* @param dev 32-bit number if the standard bus/dev/fn format which is used raw config space
*/
void showallmmio(int level, u32 dev)
{
u8 reg;
for(reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) {
u32 base = pci_conf1_read_config32(dev, reg);
u32 lim = pci_conf1_read_config32(dev,reg+4);
showmmio(level, reg, base, lim);
}
}
/**
* Show all pciio routing registers. This function is callable at any time.
* @param level The debug level
* @param dev 32-bit number if the standard bus/dev/fn format which is used raw config space
*/
void showallpciio(int level, u32 dev)
{
u8 reg;
for(reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) {
u32 base = pci_conf1_read_config32(dev, reg);
u32 lim = pci_conf1_read_config32(dev,reg+4);
showpciio(level, reg, base, lim);
}
}
/**
* Show all config routing registers. This function is callable at any time.
* @param level The debug level
* @param dev 32-bit number if the standard bus/dev/fn format which is used raw config space
*/
void showallconfig(int level, u32 dev)
{
u8 reg;
for(reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) {
u32 val = pci_conf1_read_config32(dev, reg);
showconfig(level, reg, val);
}
}
/**
* Show all routing registers. This function is callable at any time.
* @param level The debug level
* @param dev 32-bit number if the standard bus/dev/fn format which is used raw config space
*/
void showallroutes(int level, u32 dev)
{
showalldram(level, dev);
showallmmio(level, dev);
showallpciio(level, dev);
showallconfig(level, dev);
}