.S into the source file list, for reasons unknown, gcc only builds a .o
with the .S symbols/code in it; all the .c bits disappear.
So, a few changes:
1. add a rule for secondary.o, we're going to need it.
I like the fact that adding a .S file is inconvenient. Good.
Adding assembly should be hard.
2. Make two steps to initram .o building: first, the .c files, then any
extra .o files as specified by the mainboard Makefile
I realize this is a bit ugly, if there is a better solution, I'll take it.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1135 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1134 f3766cd6-281f-0410-b1cd-43a5c92072e9
2 size calculations.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1133 f3766cd6-281f-0410-b1cd-43a5c92072e9
does not compile, but this needed fixing anyway.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1132 f3766cd6-281f-0410-b1cd-43a5c92072e9
that has already been done by the BSP. For single processor systems the CPU
flag is always 0, BSP. This code also moves the AP stop for K8 mainboards to
after memory setup so the AP's MTRRs can be setup to match system memory.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1129 f3766cd6-281f-0410-b1cd-43a5c92072e9
stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
It also sets all system memory to WriteBack cached and sets the ROM
area to cached.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1128 f3766cd6-281f-0410-b1cd-43a5c92072e9
be passed in registers. This is good for size and speed but not good when
we call a C function from asm. Force stage1_phase1 to use stdcall and get
variables off the stack.
Note that I didn't change stage1_phase3 because it doesn't use any
variables.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1127 f3766cd6-281f-0410-b1cd-43a5c92072e9
A NAND device may never be mapped above 0xEFFFFFFF, as these addresses never reach
the NAND controller. Only NAND controller, as the only DIVIL component that is
allowed to be memory mapped, is affected - other Geode LX and CS5536 peripherals
(that are separate GLIU devices outside DIVIL component) can use addresses above
that limit (see in-code comment for details).
In combination with a new VSA2 version 1.02 or newer, this makes NAND flash
finally work in coreboot v3.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Signed-off-by: Anti Sullin <anti.sullin@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1125 f3766cd6-281f-0410-b1cd-43a5c92072e9
Trivial: constant currently not used anywhere.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1124 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Maggie Li <maggie.li@amd.com>
Reviewed-by: Zheng Bao <Zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1123 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1122 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1121 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1120 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Copying of files from other mainboards as a starting point:
amd/db800/Makefile
artecgroup/dbe62/cmos.layout
artecgroup/dbe62/dts
amd/db800/initram.c
artecgroup/dbe61/irq_tables.h
artecgroup/dbe62/stage1
* Kconfig integration. Behind CONFIG_EXPERIMENTAL for now, as the board is not in the market yet.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1119 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1117 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1116 f3766cd6-281f-0410-b1cd-43a5c92072e9
SPD_MIN_RAS_TO_CAS_DELAY is already set earlier in the list, so the alternative
constant tRCD in the end has no effect in the memory algorithm - remove them.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1115 f3766cd6-281f-0410-b1cd-43a5c92072e9
The device infrastructure already has an enabled bit, so we don't need to duplicate it in the current form.
cs5536.c:ide_init() is phase6_init, which is called only if the device is enabled, so if the device doesn't
exist, or the mainboard dts says "disabled;" for it, the init is not done and an extra conditional is not
necessary.
Adapt all cs5536 using mainboards to it (removing enable_ide variable) - artecgroup/dbe6[12] gets the whole
IDE device removed, which results in the ide_init() code not being ran as before (before it was called but
early return from enable_ide == 0, now it won't be called in the first place).
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1114 f3766cd6-281f-0410-b1cd-43a5c92072e9
This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better.
It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late
before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2
before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it
enabled in VSA2.
It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch,
but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the
VSA2 bug suggests something further will still need fixing. There are also more potential opportunities
to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup
actually works right in the current form.
Also corrected the documentation of ide_init() to match current reality.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1113 f3766cd6-281f-0410-b1cd-43a5c92072e9
It removes processors from the list of devices on the domain's bus so
that pci_scan_bus won't disable them, then scans for them, then puts
them back. There are lots of other ways to do this, but this one
seemed minimally invasive and ends up with a correct tree.
The dts fixups I should have put in with the other K8 patch for the
new resource allocator. I went to the v2 Config.lb files and tried to
get them as complete as possible.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1109 f3766cd6-281f-0410-b1cd-43a5c92072e9
warning that Phase 1 is obsolete if anyone implements one.
The only difference between the Phase 2 and Phase 6 implementations is that
phase2_fixup is always called if it's defined, but phase6_init is only called if
the device is enabled.
Note that any devices not found in the tree will not have their init functions
called with this patch. I think that's a good thing, but it will require some
dts fixes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1108 f3766cd6-281f-0410-b1cd-43a5c92072e9
src/northbridge/intel/i945/ich7.h:
Thanks to Uwe Hermann for spotting this typo.
src/southbridge/intel/i82801gx/i82801gx_lpc.c:
The enable_hpet() code in intel/i82801gx will not work with the
ICH7 southbridge (but it might work with ICH4/ICH5 or so).
The ICH7 needs a different init code. Drop the non-working code for now.
src/southbridge/intel/i82801gx/i82801gx.h:
Drop #defines for registers that are not existant on the ICH7.
Also, fix BIOS_CNTL, which is 0xdc on ICH7.
Build-tested with kontron/986lcd-m.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1107 f3766cd6-281f-0410-b1cd-43a5c92072e9
Merge some parts of the i945 review (trivial):
* fix \r\n occurence in i945 code
* drop early TOLUD write
* fix 16bit BCTRL1 access
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1106 f3766cd6-281f-0410-b1cd-43a5c92072e9
945.h: Add some more comments, align data for better readability (trivial).
Also, add missing C1DRA2 #define (as per public datasheet).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1105 f3766cd6-281f-0410-b1cd-43a5c92072e9
splits the domain and the memory controller functions into their respective
devices.
It also updates the dts for all the boards that use geodelx_video_mb.
Signed-off-by: Myles Watson <mylesgw@gmail.com>Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1103 f3766cd6-281f-0410-b1cd-43a5c92072e9
Peter has some valid points that need to be addressed in the future. See his
Ack message.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1100 f3766cd6-281f-0410-b1cd-43a5c92072e9
offset_pciio and an offset_io. This makes it easier to port things from v2.
It also updates mcp55 and some whitespace there.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1099 f3766cd6-281f-0410-b1cd-43a5c92072e9
Kconfig:
Add *_SUPPORT variables.
Add select statements for the hardware that needs them.
device/Makefile:
Test *_SUPPORT variables instead of chip names.
device/Kconfig:
Add *_PLUGIN_SUPPORT variables.
device/pci_device.c:
Conditionally include headers if *_PLUGIN_SUPPORT.
Update default drivers to depend on CONFIG_*_PLUGIN_SUPPORT.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1097 f3766cd6-281f-0410-b1cd-43a5c92072e9
northbridge functions and makes devices children of the northbridge.
northbridge/amd/k8/domain.c:
Add the functions from k8/pci.c that belong to the domain. Add
support for physical link numbers in resource indices. Combine find_iopair
and find_mempair to find_regpair.
northbridge/amd/k8/pci.c:
Remove functions that went to the domain.
device/hypertransport.c:
Add support for HT connections from devices that aren't the bus
controller.
device/hypertransport.h:
Change the prototype of hypertransport_scan_chain.
northbridge/amd/k8/pci:
Take out bridge flag.
mainboard/amd/serengeti/stage1.c
Change first register usage.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1094 f3766cd6-281f-0410-b1cd-43a5c92072e9
could be done.
northbridge/intel/i945/northbridge.dts
Remove bridge flag. Northbridges don't have children. The domains
they implement do.
northbridge/intel/i945/northbridge.c
Add IORESOURCE_BRIDGE flags and change the limit for MMIO to avoid ROM.
mainboard/kontron/986lcd-m/dts
Make PCI devices children of the domain and add a few devices.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1093 f3766cd6-281f-0410-b1cd-43a5c92072e9
file-by-file changes:
dts:
There are no bus devices, remove it. Add the northbridge devices.
Fix susbsytem_vendor and subsystem_device.
southbridge/intel/i82371eb/ide:
Make the ide enabled by default.
northbridge/intel/i440bxemulation/i440bx.c:
1. Split ops into domain and northbridge
A. Domain should have bus ops, scan_bus, etc.
B. Northbridge should have ops for its own registers.
In this case it only needs read and set resources.
functions:
i440bx_read_resources - set up the IO and VGA resources. VGA is fixed.
i440bx_ram_resources - this should be called after resource assignment.
i440bx_set_resources - call pci_set_resources then i440bx_ram_resources.
i440bx_domain_read_resources - Set up system-wide resources, and
reserve space for the local APIC. I put the IOAPIC here too,
but it belongs somewhere in the southbridge.
i440bx_domain_set_resources - Mark the domain-specific resources as
stored (In a real device you'd probably need to set some
registers here.) Call phase4_set_resources for children.
southbridge/intel/i82371eb/i82371eb.c:
1. Add ISA read and set resources to reserve legacy IO space.
- Note that since it's subtractively decoded, it doesn't need
to be stored anywhere. It needs to be marked stored so
pci_set_resource doesn't try to store it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1092 f3766cd6-281f-0410-b1cd-43a5c92072e9
This patch fixes up geode for the new resource allocator. This is the
bare minimum. I think the functions of the northbridge should be split based
on whether they are domain-specific or not.
southbridge/amd/cs5536/cs5536.c:
Change read resources to add a fixed IO resource for legacy decoding.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1091 f3766cd6-281f-0410-b1cd-43a5c92072e9
This patch makes specific devices use the updated resource allocation code.
The changes necessary are:
1. Remove all calls to compute_allocate_resources.
2. Don't store resources except in phase4_set_resources.
northbridge/amd/k8/pci.c:
Remove calls to compute_allocate_resource.
Change phase4_assign_resources to phase4_set_resources
southbridge/amd/amd8132/amd8132_bridge.c:
Remove NPUML and NPUMB.
Add a warning for bus disabling.
Remove bridge_{read|set}_resources (they were there for NPUML)
southbridge/nvidia/mcp55/lpc.c:
southbridge/amd/sb600/lpc.c:
Remove references to have_resources.
southbridge/amd/amd8111/lpc.c:
Add resources for subtractive IO and ROM.
northbridge/amd/k8/domain.c:
northbridge/intel/i440bxemulation/i440bx.c:
northbridge/amd/geodelx/geodelx.c:
northbridge/intel/i945/northbridge.c:
northbridge/via/cn700/stage2.c:
Change phase4_assign_resources->phase4_set_resources.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1090 f3766cd6-281f-0410-b1cd-43a5c92072e9
phases. One benefit of this is that it makes the call chain easier to follow.
device/device.c:
Remove references to have_resources.
Remove read_resources from compute allocate resources.
Split compute_allocate_resources into two
1. compute_resource_needs
A. Traverse the tree depth first
B. Sum resources
C. Adjust limits and bases
D. Update bridge resources sizes
2. assign_resource_values
A. Traverse the tree breadth first
B. Assign resource values
device/device_util.c:
Remove references to have_resources.
device/pci_device.c:
Remove saved values stubs (they're not needed now.)
1. Sizing function restores values
Fix 64-bit flag masking.
Add an error message for an invalid value.
Update pci_record_bridge_resource:
1. remove compute_allocate_resource call
2. remove pci_set_resource call
Update pci_bus_read_resources to read children's too.
Update pci_set_resource:
1. change logic for setting zero-size resources
A. Set range to [limit->limit-2^gran]
(Could have been any range with base > limit)
2. remove compute_allocate_resource calls
3. Change phase4_assign_resources ->phase4_set_resources
device/pci_ops.c:
Change an error message to be more helpful.
device/root_device.c:
Remove code for read_resources and set resources.
Add a .id to the ops.
include/device/device.h:
Remove have_resources.
Comment out assign_resources. I think we could comment out more here.
Add debugging function prototypes.
Change phase4_assign_resources to phase4_set_resources.
include/device/resource.h
Add a IORESOURCE_BRIDGE flag.
device/cardbus_device.c
Remove compute_allocate_resource call.
Use probe_resource (doesn't die) instead of find_resource.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1089 f3766cd6-281f-0410-b1cd-43a5c92072e9
disk and attempt to boot a linux kernel.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1087 f3766cd6-281f-0410-b1cd-43a5c92072e9
