mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
This patch adds southbridge/nvidia/ck804 from v2 minimally updated for v3.
Peter has some valid points that need to be addressed in the future. See his Ack message. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1100 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson
parent
f59b4ca24a
commit
481e85860b
32 changed files with 2975 additions and 0 deletions
3
Kconfig
3
Kconfig
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@ -123,6 +123,9 @@ config SOUTHBRIDGE_AMD_CS5536
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boolean
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config SOUTHBRIDGE_INTEL_I82371EB
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boolean
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config SOUTHBRIDGE_NVIDIA_CK804
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select PCIE_SUPPORT
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boolean
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config SOUTHBRIDGE_NVIDIA_MCP55
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select PCIE_SUPPORT
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boolean
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@ -265,6 +265,34 @@
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#define PCI_DEVICE_ID_NVIDIA_MCP55_TRIM 0x036A
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PMU 0x036B
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#define PCI_DEVICE_ID_NVIDIA_CK804_LPC 0x0050
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#define PCI_DEVICE_ID_NVIDIA_CK804_PRO 0x0051
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#define PCI_DEVICE_ID_NVIDIA_CK804_ISA 0x0051
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#define PCI_DEVICE_ID_NVIDIA_CK804_SMB 0x0052
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#define PCI_DEVICE_ID_NVIDIA_CK804_SM 0x0052
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#define PCI_DEVICE_ID_NVIDIA_CK804_ACPI 0x0052
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#define PCI_DEVICE_ID_NVIDIA_CK804_IDE 0x0053
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#define PCI_DEVICE_ID_NVIDIA_CK804_SATA0 0x0054
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#define PCI_DEVICE_ID_NVIDIA_CK804_SATA1 0x0055
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#define PCI_DEVICE_ID_NVIDIA_CK804_SATA1 0x0055
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#define PCI_DEVICE_ID_NVIDIA_CK804_ENET 0x0056
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#define PCI_DEVICE_ID_NVIDIA_CK804_NIC 0x0056
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#define PCI_DEVICE_ID_NVIDIA_CK804_ENET2 0x0057
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#define PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE 0x0057
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#define PCI_DEVICE_ID_NVIDIA_CK804_MODEM 0x0058
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#define PCI_DEVICE_ID_NVIDIA_CK804_MCI 0x0058
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#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059
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#define PCI_DEVICE_ID_NVIDIA_CK804_ACI 0x0059
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#define PCI_DEVICE_ID_NVIDIA_CK804_USB 0x005A
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#define PCI_DEVICE_ID_NVIDIA_CK804_USB2 0x005B
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#define PCI_DEVICE_ID_NVIDIA_CK804_PCI 0x005C
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#define PCI_DEVICE_ID_NVIDIA_CK804_PCIE 0x005D
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#define PCI_DEVICE_ID_NVIDIA_CK804_PCI_E 0x005D
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#define PCI_DEVICE_ID_NVIDIA_CK804_MEM 0x005E
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#define PCI_DEVICE_ID_NVIDIA_CK804_HT 0x005E
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#define PCI_DEVICE_ID_NVIDIA_CK804_TRIM 0x005f
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#define PCI_DEVICE_ID_NVIDIA_CK804_SLAVE 0x00d3
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#define PCI_VENDOR_ID_VIA 0x1106
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#define PCI_DEVICE_ID_VIA_CN700_AGP 0x0314
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#define PCI_DEVICE_ID_VIA_CN700_ERR 0x1314
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39
southbridge/nvidia/ck804/Makefile
Normal file
39
southbridge/nvidia/ck804/Makefile
Normal file
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@ -0,0 +1,39 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_CK804),y)
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STAGE2_CHIPSET_SRC += $(src)/southbridge/nvidia/ck804/ck804.c
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ifeq ($(CONFIG_PIRQ_TABLE),y)
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STAGE2_CHIPSET_SRC += $(src)/southbridge/nvidia/ck804/irq_tables.c
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endif
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STAGE2_CHIPSET_SRC += $(src)/southbridge/nvidia/ck804/ide.c \
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$(src)/southbridge/nvidia/ck804/pci.c \
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$(src)/southbridge/nvidia/ck804/lpc.c \
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$(src)/southbridge/nvidia/ck804/pcie.c \
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$(src)/southbridge/nvidia/ck804/sata.c \
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$(src)/southbridge/nvidia/ck804/smbus.c \
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$(src)/southbridge/nvidia/ck804/usb.c \
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$(src)/southbridge/nvidia/ck804/usb2.c
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endif
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182
southbridge/nvidia/ck804/ck804.c
Normal file
182
southbridge/nvidia/ck804/ck804.c
Normal file
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@ -0,0 +1,182 @@
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/*
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* Copyright 2004 Tyan Computer
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* by yhlu@tyan.com
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*/
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#include <console.h>
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#include <io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "ck804.h"
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static u32 final_reg;
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void ck804_set_subsystem(struct device *dev, u16 vendor, u16 device)
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{
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pci_write_config32(dev, 0x40, (device << 16) | vendor);
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}
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static struct device * find_lpc_dev(struct device * dev, unsigned devfn)
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{
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struct device * lpc_dev;
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lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
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if (!lpc_dev)
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return lpc_dev;
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if ((lpc_dev->id.pci.vendor != PCI_VENDOR_ID_NVIDIA)
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|| ((lpc_dev->id.pci.device != PCI_DEVICE_ID_NVIDIA_CK804_LPC)
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&& (lpc_dev->id.pci.device != PCI_DEVICE_ID_NVIDIA_CK804_PRO)
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&& (lpc_dev->id.pci.device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE)))
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{
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u32 id;
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id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
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if ((id != (PCI_VENDOR_ID_NVIDIA |
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(PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16)))
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&& (id != (PCI_VENDOR_ID_NVIDIA |
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(PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16)))
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&& (id != (PCI_VENDOR_ID_NVIDIA |
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(PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16))))
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{
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lpc_dev = 0;
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}
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}
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return lpc_dev;
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}
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void ck804_enable(struct device * dev)
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{
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struct device * lpc_dev;
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unsigned index = 0, index2 = 0;
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u32 vendorid;
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u16 deviceid, devfn;
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u32 reg_old, reg;
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u8 byte;
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if (dev->id.pci.device == 0x0000) {
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vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
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deviceid = (vendorid >> 16) & 0xffff;
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/* vendorid &= 0xffff; */
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} else {
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/* vendorid = dev->id.pci.vendor; */
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deviceid = dev->id.pci.device;
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}
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devfn = (dev->path.pci.devfn) & ~7;
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switch (deviceid) {
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case PCI_DEVICE_ID_NVIDIA_CK804_SM:
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index = 16;
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break;
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case PCI_DEVICE_ID_NVIDIA_CK804_USB:
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devfn -= (1 << 3);
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index = 8;
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break;
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case PCI_DEVICE_ID_NVIDIA_CK804_USB2:
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devfn -= (1 << 3);
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index = 20;
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break;
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case PCI_DEVICE_ID_NVIDIA_CK804_NIC:
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devfn -= (9 << 3);
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index = 10;
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break;
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case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE:
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devfn -= (9 << 3);
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index = 10;
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break;
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case PCI_DEVICE_ID_NVIDIA_CK804_ACI:
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devfn -= (3 << 3);
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index = 12;
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break;
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case PCI_DEVICE_ID_NVIDIA_CK804_MCI:
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devfn -= (3 << 3);
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index = 13;
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break;
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case PCI_DEVICE_ID_NVIDIA_CK804_IDE:
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devfn -= (5 << 3);
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index = 14;
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break;
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case PCI_DEVICE_ID_NVIDIA_CK804_SATA0:
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devfn -= (6 << 3);
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index = 22;
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break;
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case PCI_DEVICE_ID_NVIDIA_CK804_SATA1:
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devfn -= (7 << 3);
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index = 18;
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break;
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case PCI_DEVICE_ID_NVIDIA_CK804_PCI:
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devfn -= (8 << 3);
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index = 15;
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break;
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case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E:
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devfn -= (0xa << 3);
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index2 = 19;
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break;
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default:
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index = 0;
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}
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if (index2 != 0) {
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int i;
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for (i = 0; i < 4; i++) {
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lpc_dev = find_lpc_dev(dev, devfn - (i << 3));
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if (!lpc_dev)
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continue;
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index2 -= i;
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break;
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}
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if (lpc_dev) {
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reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
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if (!dev->enabled)
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reg |= (1 << index2);
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if (reg != reg_old)
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pci_write_config32(lpc_dev, 0xe4, reg);
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}
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index2 = 0;
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return;
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}
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lpc_dev = find_lpc_dev(dev, devfn);
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if (!lpc_dev)
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return;
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if (index == 0) {
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final_reg = pci_read_config32(lpc_dev, 0xe8);
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final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 10)
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| (1 << 12) | (1 << 13) | (1 << 14) | (1 << 22)
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| (1 << 18) | (1 << 15));
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pci_write_config32(lpc_dev, 0xe8, final_reg);
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reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
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reg |= (1 << 20);
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if (reg != reg_old)
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pci_write_config32(lpc_dev, 0xe4, reg);
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byte = pci_read_config8(lpc_dev, 0x74);
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byte |= ((1 << 1));
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pci_write_config8(dev, 0x74, byte);
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byte = pci_read_config8(lpc_dev, 0xdd);
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byte |= ((1 << 0) | (1 << 3));
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pci_write_config8(dev, 0xdd, byte);
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return;
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}
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if (!dev->enabled)
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final_reg |= (1 << index);
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if (index == 10) {
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reg_old = pci_read_config32(lpc_dev, 0xe8);
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if (final_reg != reg_old)
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pci_write_config32(lpc_dev, 0xe8, final_reg);
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}
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}
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struct pci_operations ck804_ops_pci = {
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.set_subsystem = ck804_set_subsystem,
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};
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11
southbridge/nvidia/ck804/ck804.h
Normal file
11
southbridge/nvidia/ck804/ck804.h
Normal file
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@ -0,0 +1,11 @@
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#ifndef CK804_H
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#define CK804_H
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#include <device/device.h>
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#include <device/pci.h>
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void ck804_enable(struct device *dev);
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extern struct pci_operations ck804_ops_pci;
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#endif
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57
southbridge/nvidia/ck804/ck804_ac97.c
Normal file
57
southbridge/nvidia/ck804/ck804_ac97.c
Normal file
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@ -0,0 +1,57 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2004 Tyan Computer
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* by yhlu@tyan.com
|
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
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#include <types.h>
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#include <console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "ck804.h"
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struct device_operations ac97audio = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
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.device = PCI_DEVICE_ID_NVIDIA_CK804_ACI}}},
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.constructor = default_device_constructor,
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.phase3_chip_setup_dev = ck804_enable,
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.phase3_scan = NULL,
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.phase4_read_resources = pci_dev_read_resources,
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.phase4_set_resources = pci_set_resources,
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.phase5_enable_resources = pci_dev_enable_resources,
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.phase6_init = NULL,
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.ops_pci = &ck804_ops_pci,
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};
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struct device_operations ac97modem = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
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.device = PCI_DEVICE_ID_NVIDIA_CK804_MCI}}},
|
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.constructor = default_device_constructor,
|
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.phase3_chip_setup_dev = ck804_enable,
|
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.phase3_scan = NULL,
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.phase4_read_resources = pci_dev_read_resources,
|
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.phase4_set_resources = pci_set_resources,
|
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.phase5_enable_resources = pci_dev_enable_resources,
|
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.phase6_init = NULL,
|
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.ops_pci = &ck804_ops_pci,
|
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};
|
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|
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42
southbridge/nvidia/ck804/ck804_ht.c
Normal file
42
southbridge/nvidia/ck804/ck804_ht.c
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "ck804.h"
|
||||
|
||||
struct device_operations ck804_ht_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_CK804_HT}}},
|
||||
.phase3_chip_setup_dev = ck804_enable,
|
||||
.phase3_scan = NULL,
|
||||
.phase4_read_resources = pci_dev_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
.phase5_enable_resources = pci_dev_enable_resources,
|
||||
.phase6_init = NULL,
|
||||
.ops_pci = &ck804_ops_pci,
|
||||
};
|
||||
|
||||
143
southbridge/nvidia/ck804/ck804_nic.c
Normal file
143
southbridge/nvidia/ck804/ck804_nic.c
Normal file
|
|
@ -0,0 +1,143 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/smbus.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <io.h>
|
||||
#include "ck804.h"
|
||||
|
||||
static void nic_init(struct device *dev)
|
||||
{
|
||||
u32 dword, old, mac_h, mac_l;
|
||||
int eeprom_valid = 0;
|
||||
struct southbridge_nvidia_ck804_config *conf;
|
||||
static u32 nic_index = 0;
|
||||
u8 *base;
|
||||
struct resource *res;
|
||||
|
||||
res = find_resource(dev, 0x10);
|
||||
base = res->base;
|
||||
|
||||
#define NvRegPhyInterface 0xC0
|
||||
#define PHY_RGMII 0x10000000
|
||||
|
||||
writel(PHY_RGMII, base + NvRegPhyInterface);
|
||||
|
||||
old = dword = pci_read_config32(dev, 0x30);
|
||||
dword &= ~(0xf);
|
||||
dword |= 0xf;
|
||||
if (old != dword)
|
||||
pci_write_config32(dev, 0x30, dword);
|
||||
|
||||
conf = dev->chip_info;
|
||||
|
||||
if (conf->mac_eeprom_smbus != 0) {
|
||||
/* Read MAC address from EEPROM at first. */
|
||||
struct device *dev_eeprom;
|
||||
dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus,
|
||||
conf->mac_eeprom_addr);
|
||||
|
||||
if (dev_eeprom) {
|
||||
/* If that is valid we will use that. */
|
||||
unsigned char dat[6];
|
||||
int i, status;
|
||||
for (i = 0; i < 6; i++) {
|
||||
status = smbus_read_byte(dev_eeprom, i);
|
||||
if (status < 0)
|
||||
break;
|
||||
dat[i] = status & 0xff;
|
||||
}
|
||||
if (status >= 0) {
|
||||
mac_l = 0;
|
||||
for (i = 3; i >= 0; i--) {
|
||||
mac_l <<= 8;
|
||||
mac_l += dat[i];
|
||||
}
|
||||
if (mac_l != 0xffffffff) {
|
||||
mac_l += nic_index;
|
||||
mac_h = 0;
|
||||
for (i = 5; i >= 4; i--) {
|
||||
mac_h <<= 8;
|
||||
mac_h += dat[i];
|
||||
}
|
||||
eeprom_valid = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* If that is invalid we will read that from romstrap. */
|
||||
if (!eeprom_valid) {
|
||||
unsigned long mac_pos;
|
||||
mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */
|
||||
mac_l = readl(mac_pos) + nic_index;
|
||||
mac_h = readl(mac_pos + 4);
|
||||
}
|
||||
#if 1
|
||||
/* Set that into NIC MMIO. */
|
||||
#define NvRegMacAddrA 0xA8
|
||||
#define NvRegMacAddrB 0xAC
|
||||
writel(mac_l, base + NvRegMacAddrA);
|
||||
writel(mac_h, base + NvRegMacAddrB);
|
||||
#else
|
||||
/* Set that into NIC. */
|
||||
pci_write_config32(dev, 0xa8, mac_l);
|
||||
pci_write_config32(dev, 0xac, mac_h);
|
||||
#endif
|
||||
|
||||
nic_index++;
|
||||
|
||||
#if CONFIG_PCI_ROM_RUN == 1
|
||||
pci_dev_init(dev); /* It will init Option ROM. */
|
||||
#endif
|
||||
}
|
||||
|
||||
struct device_operations ck804_nic_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_CK804_NIC}}},
|
||||
.phase3_chip_setup_dev = ck804_enable,
|
||||
.phase3_scan = NULL,
|
||||
.phase4_read_resources = pci_dev_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
.phase5_enable_resources = pci_dev_enable_resources,
|
||||
.phase6_init = nic_init,
|
||||
.ops_pci = &ck804_ops_pci,
|
||||
};
|
||||
|
||||
struct device_operations ck804_nic_bridge_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE}}},
|
||||
.phase3_chip_setup_dev = ck804_enable,
|
||||
.phase3_scan = NULL,
|
||||
.phase4_read_resources = pci_dev_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
.phase5_enable_resources = pci_dev_enable_resources,
|
||||
.phase6_init = nic_init,
|
||||
.ops_pci = &ck804_ops_pci,
|
||||
};
|
||||
|
||||
39
southbridge/nvidia/ck804/ck804_reset.c
Normal file
39
southbridge/nvidia/ck804/ck804_reset.c
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
*/
|
||||
|
||||
#include <io.h>
|
||||
|
||||
#define PCI_DEV(BUS, DEV, FN) ( \
|
||||
(((BUS) & 0xFFF) << 20) | \
|
||||
(((DEV) & 0x1F) << 15) | \
|
||||
(((FN) & 0x7) << 12))
|
||||
|
||||
typedef unsigned device_t;
|
||||
|
||||
static void pci_write_config32(device_t dev, unsigned where, unsigned value)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = (dev >> 4) | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
outl(value, 0xCFC);
|
||||
}
|
||||
|
||||
static unsigned pci_read_config32(device_t dev, unsigned where)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = (dev >> 4) | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
return inl(0xCFC);
|
||||
}
|
||||
|
||||
#include "../../../northbridge/amd/amdk8/reset_test.c"
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
/* Try rebooting through port 0xcf9. */
|
||||
outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
|
||||
outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
|
||||
}
|
||||
32
southbridge/nvidia/ck804/ck804_smbus.h
Normal file
32
southbridge/nvidia/ck804/ck804_smbus.h
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
*/
|
||||
|
||||
#ifndef CK804_SMBUS_H
|
||||
#define CK804_SMBUS_H
|
||||
|
||||
#include <device/smbus_def.h>
|
||||
#include <io.h>
|
||||
|
||||
#define SMBHSTSTAT 0x1
|
||||
#define SMBHSTPRTCL 0x0
|
||||
#define SMBHSTCMD 0x3
|
||||
#define SMBXMITADD 0x2
|
||||
#define SMBHSTDAT0 0x4
|
||||
#define SMBHSTDAT1 0x5
|
||||
|
||||
/*
|
||||
* Between 1-10 seconds, We should never timeout normally.
|
||||
* Longer than this is just painful when a timeout condition occurs.
|
||||
*/
|
||||
#define SMBUS_TIMEOUT (100 * 1000 * 10)
|
||||
|
||||
int do_smbus_write_byte(unsigned smbus_io_base, unsigned device,
|
||||
unsigned address, unsigned char val);
|
||||
|
||||
int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
|
||||
unsigned address);
|
||||
|
||||
#endif
|
||||
|
||||
85
southbridge/nvidia/ck804/ide.c
Normal file
85
southbridge/nvidia/ck804/ide.c
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <console.h>
|
||||
#include <config.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <statictree.h>
|
||||
#include "ck804.h"
|
||||
|
||||
static void ide_init(struct device *dev)
|
||||
{
|
||||
struct southbridge_nvidia_ck804_ide_config *conf;
|
||||
u32 dword;
|
||||
u16 word;
|
||||
u8 byte;
|
||||
|
||||
conf = dev->device_configuration;
|
||||
|
||||
word = pci_read_config16(dev, 0x50);
|
||||
/* Ensure prefetch is disabled. */
|
||||
word &= ~((1 << 15) | (1 << 13));
|
||||
if (conf->ide1_enable) {
|
||||
/* Enable secondary IDE interface. */
|
||||
word |= (1 << 0);
|
||||
printk(BIOS_DEBUG, "IDE1 \t");
|
||||
}
|
||||
if (conf->ide0_enable) {
|
||||
/* Enable primary IDE interface. */
|
||||
word |= (1 << 1);
|
||||
printk(BIOS_DEBUG, "IDE0\n");
|
||||
}
|
||||
|
||||
word |= (1 << 12);
|
||||
word |= (1 << 14);
|
||||
|
||||
pci_write_config16(dev, 0x50, word);
|
||||
|
||||
byte = 0x20; /* Latency: 64 --> 32 */
|
||||
pci_write_config8(dev, 0xd, byte);
|
||||
|
||||
dword = pci_read_config32(dev, 0xf8);
|
||||
dword |= 12;
|
||||
pci_write_config32(dev, 0xf8, dword);
|
||||
|
||||
#ifdef CONFIG_PCI_OPTION_ROM_RUN
|
||||
pci_dev_init(dev);
|
||||
#endif
|
||||
}
|
||||
|
||||
struct device_operations ck804_ide_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_CK804_IDE}}},
|
||||
.constructor = default_device_constructor,
|
||||
.phase3_chip_setup_dev = ck804_enable,
|
||||
.phase3_scan = NULL,
|
||||
.phase4_read_resources = pci_dev_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
.phase5_enable_resources = pci_dev_enable_resources,
|
||||
.phase6_init = ide_init,
|
||||
//.ops_pci = &ck804_ops_pci,
|
||||
};
|
||||
|
||||
25
southbridge/nvidia/ck804/ide.dts
Normal file
25
southbridge/nvidia/ck804/ide.dts
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
{
|
||||
device_operations = "ck804_ide_ops";
|
||||
ide0_enable = "1";
|
||||
ide1_enable = "1";
|
||||
};
|
||||
430
southbridge/nvidia/ck804/lpc.c
Normal file
430
southbridge/nvidia/ck804/lpc.c
Normal file
|
|
@ -0,0 +1,430 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* (C) 2003 Linux Networx, SuSE Linux AG
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
* 2006.1 yhlu add dest apicid for IRQ0
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pnp.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <mc146818rtc.h>
|
||||
#include <isa-dma.h>
|
||||
#include <lib.h>
|
||||
#include <io.h>
|
||||
#include <lapic.h>
|
||||
#include "ck804.h"
|
||||
|
||||
#define CK804_CHIP_REV 2
|
||||
|
||||
#define NMI_OFF 0
|
||||
|
||||
struct ioapicreg {
|
||||
unsigned int reg;
|
||||
unsigned int value_low, value_high;
|
||||
};
|
||||
|
||||
static struct ioapicreg ioapicregvalues[] = {
|
||||
#define ALL (0xff << 24)
|
||||
#define NONE (0)
|
||||
#define DISABLED (1 << 16)
|
||||
#define ENABLED (0 << 16)
|
||||
#define TRIGGER_EDGE (0 << 15)
|
||||
#define TRIGGER_LEVEL (1 << 15)
|
||||
#define POLARITY_HIGH (0 << 13)
|
||||
#define POLARITY_LOW (1 << 13)
|
||||
#define PHYSICAL_DEST (0 << 11)
|
||||
#define LOGICAL_DEST (1 << 11)
|
||||
#define ExtINT (7 << 8)
|
||||
#define NMI (4 << 8)
|
||||
#define SMI (2 << 8)
|
||||
#define INT (1 << 8)
|
||||
/* IO-APIC virtual wire mode configuration */
|
||||
/* mask, trigger, polarity, destination, delivery, vector */
|
||||
{0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
|
||||
{1, DISABLED, NONE},
|
||||
{2, DISABLED, NONE},
|
||||
{3, DISABLED, NONE},
|
||||
{4, DISABLED, NONE},
|
||||
{5, DISABLED, NONE},
|
||||
{6, DISABLED, NONE},
|
||||
{7, DISABLED, NONE},
|
||||
{8, DISABLED, NONE},
|
||||
{9, DISABLED, NONE},
|
||||
{10, DISABLED, NONE},
|
||||
{11, DISABLED, NONE},
|
||||
{12, DISABLED, NONE},
|
||||
{13, DISABLED, NONE},
|
||||
{14, DISABLED, NONE},
|
||||
{15, DISABLED, NONE},
|
||||
{16, DISABLED, NONE},
|
||||
{17, DISABLED, NONE},
|
||||
{18, DISABLED, NONE},
|
||||
{19, DISABLED, NONE},
|
||||
{20, DISABLED, NONE},
|
||||
{21, DISABLED, NONE},
|
||||
{22, DISABLED, NONE},
|
||||
{23, DISABLED, NONE},
|
||||
/* Be careful and don't write past the end... */
|
||||
};
|
||||
|
||||
static void setup_ioapic(unsigned long ioapic_base)
|
||||
{
|
||||
int i;
|
||||
unsigned long value_low, value_high;
|
||||
/* unsigned long ioapic_base = 0xfec00000; */
|
||||
volatile unsigned long *l;
|
||||
struct ioapicreg *a = ioapicregvalues;
|
||||
|
||||
ioapicregvalues[0].value_high = lapicid() << (56 - 32);
|
||||
|
||||
l = (unsigned long *)ioapic_base;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) {
|
||||
l[0] = (a->reg * 2) + 0x10;
|
||||
l[4] = a->value_low;
|
||||
value_low = l[4];
|
||||
l[0] = (a->reg * 2) + 0x11;
|
||||
l[4] = a->value_high;
|
||||
value_high = l[4];
|
||||
if ((i == 0) && (value_low == 0xffffffff)) {
|
||||
printk(BIOS_INFO, "IO APIC not responding.\n");
|
||||
return;
|
||||
}
|
||||
printk(BIOS_SPEW, "for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
|
||||
a->reg, a->value_low, a->value_high);
|
||||
}
|
||||
}
|
||||
|
||||
// 0x7a or e3
|
||||
#define PREVIOUS_POWER_STATE 0x7A
|
||||
|
||||
#define MAINBOARD_POWER_OFF 0
|
||||
#define MAINBOARD_POWER_ON 1
|
||||
#define SLOW_CPU_OFF 0
|
||||
#define SLOW_CPU__ON 1
|
||||
|
||||
#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
|
||||
#endif
|
||||
|
||||
static void lpc_common_init(struct device * dev)
|
||||
{
|
||||
u8 byte;
|
||||
u32 dword;
|
||||
|
||||
/* I/O APIC initialization */
|
||||
byte = pci_read_config8(dev, 0x74);
|
||||
byte |= (1 << 0); /* Enable APIC. */
|
||||
pci_write_config8(dev, 0x74, byte);
|
||||
dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
|
||||
|
||||
setup_ioapic(dword);
|
||||
|
||||
#if 1
|
||||
dword = pci_read_config32(dev, 0xe4);
|
||||
dword |= (1 << 23);
|
||||
pci_write_config32(dev, 0xe4, dword);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void lpc_slave_init(struct device * dev)
|
||||
{
|
||||
lpc_common_init(dev);
|
||||
}
|
||||
|
||||
static void rom_dummy_write(struct device * dev)
|
||||
{
|
||||
u8 old, new;
|
||||
u8 *p;
|
||||
|
||||
old = pci_read_config8(dev, 0x88);
|
||||
new = old | 0xc0;
|
||||
if (new != old)
|
||||
pci_write_config8(dev, 0x88, new);
|
||||
/* Enable write. */
|
||||
old = pci_read_config8(dev, 0x6d);
|
||||
new = old | 0x01;
|
||||
if (new != old)
|
||||
pci_write_config8(dev, 0x6d, new);
|
||||
|
||||
/* Dummy write. */
|
||||
p = (u8 *) 0xffffffe0;
|
||||
old = 0;
|
||||
*p = old;
|
||||
old = *p;
|
||||
|
||||
/* Disable write. */
|
||||
old = pci_read_config8(dev, 0x6d);
|
||||
new = old & 0xfe;
|
||||
if (new != old)
|
||||
pci_write_config8(dev, 0x6d, new);
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void enable_hpet(struct device *dev)
|
||||
{
|
||||
unsigned long hpet_address;
|
||||
|
||||
pci_write_config32(dev, 0x44, 0xfed00001);
|
||||
hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
|
||||
printk(BIOS_DEBUG, "Enabling HPET @0x%x\n", hpet_address);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void lpc_init(struct device * dev)
|
||||
{
|
||||
u8 byte, byte_old;
|
||||
int on, nmi_option;
|
||||
|
||||
lpc_common_init(dev);
|
||||
|
||||
#if CK804_CHIP_REV==1
|
||||
if (dev->bus->secondary != 1)
|
||||
return;
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
/* Posted memory write enable */
|
||||
byte = pci_read_config8(dev, 0x46);
|
||||
pci_write_config8(dev, 0x46, byte | (1 << 0));
|
||||
#endif
|
||||
|
||||
/* power after power fail */
|
||||
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
|
||||
get_option(&on, "power_on_after_fail");
|
||||
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
|
||||
byte &= ~0x40;
|
||||
if (!on)
|
||||
byte |= 0x40;
|
||||
pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
|
||||
printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
|
||||
|
||||
/* Throttle the CPU speed down for testing. */
|
||||
on = SLOW_CPU_OFF;
|
||||
get_option(&on, "slow_cpu");
|
||||
if (on) {
|
||||
u16 pm10_bar;
|
||||
u32 dword;
|
||||
pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00);
|
||||
outl(((on << 1) + 0x10), (pm10_bar + 0x10));
|
||||
dword = inl(pm10_bar + 0x10);
|
||||
on = 8 - on;
|
||||
printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
|
||||
(on * 12) + (on >> 1), (on & 1) * 5);
|
||||
}
|
||||
#if 0
|
||||
// default is enabled
|
||||
/* Enable Port 92 fast reset. */
|
||||
byte = pci_read_config8(dev, 0xe8);
|
||||
byte |= ~(1 << 3);
|
||||
pci_write_config8(dev, 0xe8, byte);
|
||||
#endif
|
||||
|
||||
/* Enable Error reporting. */
|
||||
/* Set up sync flood detected. */
|
||||
byte = pci_read_config8(dev, 0x47);
|
||||
byte |= (1 << 1);
|
||||
pci_write_config8(dev, 0x47, byte);
|
||||
|
||||
/* Set up NMI on errors. */
|
||||
byte = inb(0x70); /* RTC70 */
|
||||
byte_old = byte;
|
||||
nmi_option = NMI_OFF;
|
||||
get_option(&nmi_option, "nmi");
|
||||
if (nmi_option) {
|
||||
byte &= ~(1 << 7); /* Set NMI. */
|
||||
} else {
|
||||
byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
|
||||
}
|
||||
if (byte != byte_old)
|
||||
outb(0x70, byte);
|
||||
|
||||
/* Initialize the real time clock (RTC). */
|
||||
rtc_init(0);
|
||||
|
||||
/* Initialize ISA DMA. */
|
||||
isa_dma_init();
|
||||
|
||||
/* Initialize the High Precision Event Timers (HPET). */
|
||||
/* enable_hpet(dev); */
|
||||
|
||||
rom_dummy_write(dev);
|
||||
}
|
||||
|
||||
static void ck804_lpc_read_resources(struct device * dev)
|
||||
{
|
||||
struct resource *res;
|
||||
unsigned long index;
|
||||
|
||||
/* Get the normal PCI resources of this device. */
|
||||
/* We got one for APIC, or one more for TRAP. */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */
|
||||
for (index = 0x60; index <= 0x68; index += 4) /* We got another 3. */
|
||||
pci_get_resource(dev, index);
|
||||
compact_resources(dev);
|
||||
|
||||
/* Add an extra subtractive resource for both memory and I/O. */
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
|
||||
res->flags =
|
||||
IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
||||
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
|
||||
res->flags =
|
||||
IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable resources for children devices.
|
||||
*
|
||||
* This function is called by the global enable_resources() indirectly via the
|
||||
* device_operation::enable_resources() method of devices.
|
||||
*
|
||||
* Indirect mutual recursion:
|
||||
* enable_childrens_resources() -> enable_resources()
|
||||
* enable_resources() -> device_operation::enable_resources()
|
||||
* device_operation::enable_resources() -> enable_children_resources()
|
||||
*
|
||||
* @param dev The device whose children's resources are to be enabled.
|
||||
*/
|
||||
static void ck804_lpc_enable_childrens_resources(struct device * dev)
|
||||
{
|
||||
unsigned link;
|
||||
u32 reg, reg_var[4];
|
||||
int i, var_num = 0;
|
||||
|
||||
reg = pci_read_config32(dev, 0xa0);
|
||||
|
||||
for (link = 0; link < dev->links; link++) {
|
||||
struct device * child;
|
||||
for (child = dev->link[link].children; child; child = child->sibling) {
|
||||
if (child->path.type == DEVICE_PATH_PNP) {
|
||||
for (i = 0; i < child->resources; i++) {
|
||||
struct resource *res;
|
||||
resource_t base, end;
|
||||
res = &child->resource[i];
|
||||
if (!(res->flags & IORESOURCE_IO))
|
||||
continue;
|
||||
base = res->base;
|
||||
end = resource_end(res);
|
||||
printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08llx, end=0x%08llx\n", dev_path(child), base, end);
|
||||
switch (base) {
|
||||
case 0x3f8: // COM1
|
||||
reg |= (1 << 0);
|
||||
break;
|
||||
case 0x2f8: // COM2
|
||||
reg |= (1 << 1);
|
||||
break;
|
||||
case 0x378: // Parallel 1
|
||||
reg |= (1 << 24);
|
||||
break;
|
||||
case 0x3f0: // FD0
|
||||
reg |= (1 << 20);
|
||||
break;
|
||||
case 0x220: // Audio 0
|
||||
reg |= (1 << 8);
|
||||
break;
|
||||
case 0x300: // Midi 0
|
||||
reg |= (1 << 12);
|
||||
break;
|
||||
}
|
||||
if (base == 0x290 || base >= 0x400) {
|
||||
if (var_num >= 4)
|
||||
continue; // only 4 var ; compact them ?
|
||||
reg |= (1 << (28 + var_num));
|
||||
reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
pci_write_config32(dev, 0xa0, reg);
|
||||
for (i = 0; i < var_num; i++)
|
||||
pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]);
|
||||
}
|
||||
|
||||
static void ck804_lpc_enable_resources(struct device * dev)
|
||||
{
|
||||
pci_dev_enable_resources(dev);
|
||||
ck804_lpc_enable_childrens_resources(dev);
|
||||
enable_childrens_resources(dev);
|
||||
}
|
||||
|
||||
void lpci_set_subsystem(struct device *dev, u16 vendor, u16 device)
|
||||
{
|
||||
pci_write_config32(dev, 0x40,
|
||||
((device & 0xffff) << 16) | (vendor & 0xffff));
|
||||
}
|
||||
|
||||
static struct pci_operations lops_pci = {
|
||||
.set_subsystem = lpci_set_subsystem,
|
||||
};
|
||||
|
||||
struct device_operations ck804_lpc_pro_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_CK804_PRO}}},
|
||||
.constructor = default_device_constructor,
|
||||
.phase3_scan = scan_static_bus,
|
||||
.phase4_read_resources = ck804_lpc_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
.phase5_enable_resources = ck804_lpc_enable_resources,
|
||||
.phase6_init = lpc_init,
|
||||
// .enable = ck804_enable,
|
||||
.ops_pci = &lops_pci,
|
||||
};
|
||||
|
||||
struct device_operations ck804_lpc_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_CK804_LPC}}},
|
||||
.constructor = default_device_constructor,
|
||||
.phase3_scan = scan_static_bus,
|
||||
.phase4_read_resources = ck804_lpc_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
.phase5_enable_resources = ck804_lpc_enable_resources,
|
||||
.phase6_init = lpc_init,
|
||||
// .enable = ck804_enable,
|
||||
.ops_pci = &lops_pci,
|
||||
};
|
||||
|
||||
struct device_operations ck804_lpc_slave_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE}}},
|
||||
.constructor = default_device_constructor,
|
||||
.phase3_scan = scan_static_bus,
|
||||
.phase4_read_resources = ck804_lpc_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
#if CK804_CHIP_REV == 1
|
||||
.phase5_enable_resources = ck804_lpc_enable_resources,
|
||||
.phase6_init = lpc_init,
|
||||
#else
|
||||
.phase5_enable_resources = pci_dev_enable_resources,
|
||||
.phase6_init = lpc_slave_init,
|
||||
#endif
|
||||
// .enable = ck804_enable,
|
||||
.ops_pci = &lops_pci,
|
||||
};
|
||||
24
southbridge/nvidia/ck804/lpc.dts
Normal file
24
southbridge/nvidia/ck804/lpc.dts
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
{
|
||||
device_operations = "ck804_lpc_ops";
|
||||
bridge;
|
||||
};
|
||||
93
southbridge/nvidia/ck804/pci.c
Normal file
93
southbridge/nvidia/ck804/pci.c
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "ck804.h"
|
||||
|
||||
static void pci_init(struct device *dev)
|
||||
{
|
||||
u32 dword;
|
||||
|
||||
dword = pci_read_config32(dev, 0x04);
|
||||
dword |= (1 << 8); /* System error enable */
|
||||
dword |= (1 << 30); /* Clear possible errors */
|
||||
pci_write_config32(dev, 0x04, dword);
|
||||
|
||||
#if 0
|
||||
word = pci_read_config16(dev, 0x48);
|
||||
word |= (1 << 0); /* MRL2MRM */
|
||||
word |= (1 << 2); /* MR2MRM */
|
||||
pci_write_config16(dev, 0x48, word);
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
dword = pci_read_config32(dev, 0x4c);
|
||||
dword |= 0x00440000; /* TABORT_SER_ENABLE Park Last Enable. */
|
||||
pci_write_config32(dev, 0x4c, dword);
|
||||
#endif
|
||||
|
||||
#warning 64-bit disabled here
|
||||
#if 0
|
||||
struct device * pci_domain_dev;
|
||||
struct resource *mem1, *mem2;
|
||||
pci_domain_dev = dev->bus->dev;
|
||||
|
||||
if (!pci_domain_dev)
|
||||
return; /* Impossible */
|
||||
|
||||
mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit
|
||||
mem2 = find_resource(pci_domain_dev, 2); // mem
|
||||
if (mem1->base > mem2->base) {
|
||||
dword = mem2->base & (0xffff0000UL);
|
||||
printk(BIOS_DEBUG, "PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base);
|
||||
} else {
|
||||
dword = mem1->base & (0xffff0000UL);
|
||||
printk(BIOS_DEBUG, "PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n",
|
||||
mem1->base);
|
||||
}
|
||||
#else
|
||||
dword = dev_root.resource[1].base & (0xffff0000UL);
|
||||
printk(BIOS_DEBUG, "dev_root mem base = 0x%010Lx\n",
|
||||
dev_root.resource[1].base);
|
||||
#endif
|
||||
|
||||
printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword);
|
||||
pci_write_config32(dev, 0x50, dword); /* TOM */
|
||||
}
|
||||
|
||||
struct device_operations ck804_pci_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_CK804_PCI}}},
|
||||
.phase3_chip_setup_dev = ck804_enable,
|
||||
.phase3_scan = pci_scan_bridge,
|
||||
.phase4_read_resources = pci_dev_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
.phase5_enable_resources = pci_dev_enable_resources,
|
||||
.phase6_init = pci_init,
|
||||
.ops_pci = NULL,
|
||||
};
|
||||
|
||||
24
southbridge/nvidia/ck804/pci.dts
Normal file
24
southbridge/nvidia/ck804/pci.dts
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
{
|
||||
device_operations = "ck804_pci_ops";
|
||||
bridge;
|
||||
};
|
||||
54
southbridge/nvidia/ck804/pcie.c
Normal file
54
southbridge/nvidia/ck804/pcie.c
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "ck804.h"
|
||||
|
||||
static void pcie_init(struct device *dev)
|
||||
{
|
||||
u32 dword;
|
||||
|
||||
/* Enable PCI error detecting. */
|
||||
dword = pci_read_config32(dev, 0x04);
|
||||
dword |= (1 << 8); /* System error enable */
|
||||
dword |= (1 << 30); /* Clear possible errors */
|
||||
pci_write_config32(dev, 0x04, dword);
|
||||
}
|
||||
|
||||
|
||||
struct device_operations ck804_pcie_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_CK804_PCI_E}}},
|
||||
.phase3_chip_setup_dev = ck804_enable,
|
||||
.phase3_scan = pci_scan_bridge,
|
||||
.phase4_read_resources = pci_bus_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
.phase5_enable_resources = pci_bus_enable_resources,
|
||||
.phase6_init = pcie_init,
|
||||
.ops_pci = NULL,
|
||||
};
|
||||
|
||||
24
southbridge/nvidia/ck804/pcie.dts
Normal file
24
southbridge/nvidia/ck804/pcie.dts
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
{
|
||||
device_operations = "ck804_pcie_ops";
|
||||
bridge;
|
||||
};
|
||||
189
southbridge/nvidia/ck804/sata.c
Normal file
189
southbridge/nvidia/ck804/sata.c
Normal file
|
|
@ -0,0 +1,189 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <console.h>
|
||||
#include <device/device.h>
|
||||
#include <lib.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <statictree.h>
|
||||
#include "ck804.h"
|
||||
|
||||
static void sata_com_reset(struct device *dev, unsigned reset)
|
||||
// reset = 1 : reset
|
||||
// reset = 0 : clear
|
||||
{
|
||||
u32 *base;
|
||||
u32 dword;
|
||||
int loop;
|
||||
|
||||
base = (u32 *) pci_read_config32(dev, 0x24);
|
||||
|
||||
printk(BIOS_DEBUG, "base = %p\n", base);
|
||||
|
||||
if (reset) {
|
||||
*(base + 4) = 0xffffffff;
|
||||
*(base + 0x44) = 0xffffffff;
|
||||
}
|
||||
|
||||
dword = *(base + 8);
|
||||
dword &= ~(0xf);
|
||||
dword |= reset;
|
||||
|
||||
*(base + 8) = dword;
|
||||
*(base + 0x48) = dword;
|
||||
|
||||
#if 0
|
||||
udelay(1000);
|
||||
dword &= ~(0xf);
|
||||
*(base + 8) = dword;
|
||||
*(base + 0x48) = dword;
|
||||
#endif
|
||||
|
||||
if (reset)
|
||||
return;
|
||||
|
||||
dword = *(base + 0);
|
||||
printk(BIOS_DEBUG, "*(base+0)=%08x\n", dword);
|
||||
if (dword == 0x113) {
|
||||
loop = 200000; // 2
|
||||
do {
|
||||
dword = *(base + 4);
|
||||
if ((dword & 0x10000) != 0)
|
||||
break;
|
||||
udelay(10);
|
||||
} while (--loop > 0);
|
||||
printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\n", loop, dword);
|
||||
}
|
||||
|
||||
dword = *(base + 0x40);
|
||||
printk(BIOS_DEBUG, "*(base+0x40)=%08x\n", dword);
|
||||
if (dword == 0x113) {
|
||||
loop = 200000; //2
|
||||
do {
|
||||
dword = *(base + 0x44);
|
||||
if ((dword & 0x10000) != 0)
|
||||
break;
|
||||
udelay(10);
|
||||
} while (--loop > 0);
|
||||
printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\n", loop, dword);
|
||||
}
|
||||
}
|
||||
|
||||
static void sata_init(struct device *dev)
|
||||
{
|
||||
u32 dword;
|
||||
struct southbridge_nvidia_ck804_sata_config *conf;
|
||||
|
||||
conf = dev->device_configuration;
|
||||
|
||||
dword = pci_read_config32(dev, 0x50);
|
||||
/* Ensure prefetch is disabled. */
|
||||
dword &= ~((1 << 15) | (1 << 13));
|
||||
if (conf->sata1_enable) {
|
||||
/* Enable secondary SATA interface. */
|
||||
dword |= (1 << 0);
|
||||
printk(BIOS_DEBUG, "SATA S \t");
|
||||
}
|
||||
if (conf->sata0_enable) {
|
||||
/* Enable primary SATA interface. */
|
||||
dword |= (1 << 1);
|
||||
printk(BIOS_DEBUG, "SATA P \n");
|
||||
}
|
||||
#if 0
|
||||
/* Write back */
|
||||
dword |= (1 << 12);
|
||||
dword |= (1 << 14);
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
/* ADMA */
|
||||
dword |= (1 << 16);
|
||||
dword |= (1 << 17);
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
/* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */
|
||||
dword &= ~(0x1f << 24);
|
||||
dword |= (0x15 << 24);
|
||||
#endif
|
||||
pci_write_config32(dev, 0x50, dword);
|
||||
|
||||
#if 0
|
||||
/* SLUMBER_DURING_D3 */
|
||||
dword = pci_read_config32(dev, 0x7c);
|
||||
dword &= ~(1 << 4);
|
||||
pci_write_config32(dev, 0x7c, dword);
|
||||
|
||||
dword = pci_read_config32(dev, 0xd0);
|
||||
dword &= ~(0xff << 24);
|
||||
dword |= (0x68 << 24);
|
||||
pci_write_config32(dev, 0xd0, dword);
|
||||
|
||||
dword = pci_read_config32(dev, 0xe0);
|
||||
dword &= ~(0xff << 24);
|
||||
dword |= (0x68 << 24);
|
||||
pci_write_config32(dev, 0xe0, dword);
|
||||
#endif
|
||||
|
||||
dword = pci_read_config32(dev, 0xf8);
|
||||
dword |= 2;
|
||||
pci_write_config32(dev, 0xf8, dword);
|
||||
|
||||
#if 0
|
||||
dword = pci_read_config32(dev, 0xac);
|
||||
dword &= ~((1 << 13) | (1 << 14));
|
||||
dword |= (1 << 13) | (0 << 14);
|
||||
pci_write_config32(dev, 0xac, dword);
|
||||
|
||||
sata_com_reset(dev, 1); /* For discover some s-atapi device. */
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
struct device_operations ck804_sata0_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_CK804_SATA0}}},
|
||||
.phase3_chip_setup_dev = ck804_enable,
|
||||
.phase3_scan = NULL,
|
||||
.phase4_read_resources = pci_dev_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
.phase5_enable_resources = pci_dev_enable_resources,
|
||||
.phase6_init = sata_init,
|
||||
.ops_pci = &ck804_ops_pci,
|
||||
};
|
||||
|
||||
struct device_operations ck804_sata1_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_CK804_SATA1}}},
|
||||
.phase3_chip_setup_dev = ck804_enable,
|
||||
.phase3_scan = NULL,
|
||||
.phase4_read_resources = pci_dev_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
.phase5_enable_resources = pci_dev_enable_resources,
|
||||
.phase6_init = sata_init,
|
||||
.ops_pci = &ck804_ops_pci,
|
||||
};
|
||||
|
||||
25
southbridge/nvidia/ck804/sata.dts
Normal file
25
southbridge/nvidia/ck804/sata.dts
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
{
|
||||
device_operations = "ck804_sata0_ops";
|
||||
sata0_enable = "1";
|
||||
sata1_enable = "1";
|
||||
};
|
||||
25
southbridge/nvidia/ck804/sata1.dts
Normal file
25
southbridge/nvidia/ck804/sata1.dts
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
{
|
||||
device_operations = "ck804_sata1_ops";
|
||||
sata0_enable = "1";
|
||||
sata1_enable = "1";
|
||||
};
|
||||
197
southbridge/nvidia/ck804/shared_smbus.c
Normal file
197
southbridge/nvidia/ck804/shared_smbus.c
Normal file
|
|
@ -0,0 +1,197 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <device/smbus.h>
|
||||
#include <device/smbus_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/device.h>
|
||||
#include <console.h>
|
||||
#include <io.h>
|
||||
#include "ck804_smbus.h"
|
||||
|
||||
static inline void smbus_delay(void)
|
||||
{
|
||||
outb(0x80, 0x80);
|
||||
}
|
||||
|
||||
int smbus_wait_until_ready(unsigned smbus_io_base)
|
||||
{
|
||||
unsigned long loops;
|
||||
loops = SMBUS_TIMEOUT;
|
||||
do {
|
||||
unsigned char val;
|
||||
smbus_delay();
|
||||
val = inb(smbus_io_base + SMBHSTSTAT);
|
||||
val &= 0x1f;
|
||||
if (val == 0)
|
||||
return 0;
|
||||
outb(val, smbus_io_base + SMBHSTSTAT);
|
||||
} while (--loops);
|
||||
return -2;
|
||||
}
|
||||
|
||||
int smbus_wait_until_done(unsigned smbus_io_base)
|
||||
{
|
||||
unsigned long loops;
|
||||
loops = SMBUS_TIMEOUT;
|
||||
do {
|
||||
unsigned char val;
|
||||
smbus_delay();
|
||||
val = inb(smbus_io_base + SMBHSTSTAT);
|
||||
if ((val & 0xff) != 0)
|
||||
return 0;
|
||||
} while (--loops);
|
||||
return -3;
|
||||
}
|
||||
|
||||
int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
|
||||
{
|
||||
unsigned char global_status_register, byte;
|
||||
|
||||
/* Set the device I'm talking to. */
|
||||
outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
|
||||
smbus_delay();
|
||||
|
||||
/* Set the command/address. */
|
||||
outb(0, smbus_io_base + SMBHSTCMD);
|
||||
smbus_delay();
|
||||
|
||||
/* Byte data recv */
|
||||
outb(0x05, smbus_io_base + SMBHSTPRTCL);
|
||||
smbus_delay();
|
||||
|
||||
/* Poll for transaction completion. */
|
||||
if (smbus_wait_until_done(smbus_io_base) < 0)
|
||||
return -3;
|
||||
|
||||
/* Lose check */
|
||||
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
|
||||
|
||||
/* Read results of transaction. */
|
||||
byte = inb(smbus_io_base + SMBHSTDAT0);
|
||||
|
||||
/* Lose check, otherwise it should be 0. */
|
||||
if (global_status_register != 0x80)
|
||||
return -1;
|
||||
|
||||
return byte;
|
||||
}
|
||||
|
||||
int do_smbus_send_byte(unsigned smbus_io_base, unsigned device,
|
||||
unsigned char val)
|
||||
{
|
||||
unsigned global_status_register;
|
||||
|
||||
outb(val, smbus_io_base + SMBHSTDAT0);
|
||||
smbus_delay();
|
||||
|
||||
/* Set the device I'm talking to. */
|
||||
outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
|
||||
smbus_delay();
|
||||
|
||||
outb(0, smbus_io_base + SMBHSTCMD);
|
||||
smbus_delay();
|
||||
|
||||
/* Set up for a byte data write. */
|
||||
outb(0x04, smbus_io_base + SMBHSTPRTCL);
|
||||
smbus_delay();
|
||||
|
||||
/* Poll for transaction completion. */
|
||||
if (smbus_wait_until_done(smbus_io_base) < 0)
|
||||
return -3;
|
||||
|
||||
/* Lose check */
|
||||
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
|
||||
|
||||
if (global_status_register != 0x80)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
|
||||
unsigned address)
|
||||
{
|
||||
unsigned char global_status_register, byte;
|
||||
|
||||
/* Set the device I'm talking to. */
|
||||
outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
|
||||
smbus_delay();
|
||||
|
||||
/* Set the command/address. */
|
||||
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
|
||||
smbus_delay();
|
||||
|
||||
/* Byte data read */
|
||||
outb(0x07, smbus_io_base + SMBHSTPRTCL);
|
||||
smbus_delay();
|
||||
|
||||
/* Poll for transaction completion. */
|
||||
if (smbus_wait_until_done(smbus_io_base) < 0)
|
||||
return -3;
|
||||
|
||||
/* Lose check */
|
||||
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
|
||||
|
||||
/* Read results of transaction. */
|
||||
byte = inb(smbus_io_base + SMBHSTDAT0);
|
||||
|
||||
/* Lose check, otherwise it should be 0. */
|
||||
if (global_status_register != 0x80)
|
||||
return -1;
|
||||
|
||||
return byte;
|
||||
}
|
||||
|
||||
int do_smbus_write_byte(unsigned smbus_io_base, unsigned device,
|
||||
unsigned address, unsigned char val)
|
||||
{
|
||||
unsigned global_status_register;
|
||||
|
||||
outb(val, smbus_io_base + SMBHSTDAT0);
|
||||
smbus_delay();
|
||||
|
||||
/* Set the device I'm talking to. */
|
||||
outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
|
||||
smbus_delay();
|
||||
|
||||
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
|
||||
smbus_delay();
|
||||
|
||||
/* Set up for a byte data write. */
|
||||
outb(0x06, smbus_io_base + SMBHSTPRTCL);
|
||||
smbus_delay();
|
||||
|
||||
/* Poll for transaction completion. */
|
||||
if (smbus_wait_until_done(smbus_io_base) < 0)
|
||||
return -3;
|
||||
|
||||
/* Lose check */
|
||||
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
|
||||
|
||||
if (global_status_register != 0x80)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
299
southbridge/nvidia/ck804/smbus.c
Normal file
299
southbridge/nvidia/ck804/smbus.c
Normal file
|
|
@ -0,0 +1,299 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <device/smbus.h>
|
||||
#include <device/smbus_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/device.h>
|
||||
#include <console.h>
|
||||
#include <io.h>
|
||||
#include "ck804.h"
|
||||
#include "ck804_smbus.h"
|
||||
|
||||
static inline void smbus_delay(void)
|
||||
{
|
||||
outb(0x80, 0x80);
|
||||
}
|
||||
|
||||
int smbus_wait_until_ready(unsigned smbus_io_base)
|
||||
{
|
||||
unsigned long loops;
|
||||
loops = SMBUS_TIMEOUT;
|
||||
do {
|
||||
unsigned char val;
|
||||
smbus_delay();
|
||||
val = inb(smbus_io_base + SMBHSTSTAT);
|
||||
val &= 0x1f;
|
||||
if (val == 0)
|
||||
return 0;
|
||||
outb(val, smbus_io_base + SMBHSTSTAT);
|
||||
} while (--loops);
|
||||
return -2;
|
||||
}
|
||||
|
||||
int smbus_wait_until_done(unsigned smbus_io_base)
|
||||
{
|
||||
unsigned long loops;
|
||||
loops = SMBUS_TIMEOUT;
|
||||
do {
|
||||
unsigned char val;
|
||||
smbus_delay();
|
||||
val = inb(smbus_io_base + SMBHSTSTAT);
|
||||
if ((val & 0xff) != 0)
|
||||
return 0;
|
||||
} while (--loops);
|
||||
return -3;
|
||||
}
|
||||
|
||||
int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
|
||||
{
|
||||
unsigned char global_status_register, byte;
|
||||
|
||||
#if 0
|
||||
/* Not needed, upon write to PRTCL, the status will be auto-cleared. */
|
||||
if (smbus_wait_until_ready(smbus_io_base) < 0)
|
||||
return -2;
|
||||
#endif
|
||||
|
||||
/* Set the device I'm talking to. */
|
||||
outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
|
||||
smbus_delay();
|
||||
|
||||
/* Set the command/address. */
|
||||
outb(0, smbus_io_base + SMBHSTCMD);
|
||||
smbus_delay();
|
||||
|
||||
/* Byte data recv */
|
||||
outb(0x05, smbus_io_base + SMBHSTPRTCL);
|
||||
smbus_delay();
|
||||
|
||||
/* Poll for transaction completion. */
|
||||
if (smbus_wait_until_done(smbus_io_base) < 0)
|
||||
return -3;
|
||||
|
||||
/* Lose check */
|
||||
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
|
||||
|
||||
/* Read results of transaction. */
|
||||
byte = inb(smbus_io_base + SMBHSTDAT0);
|
||||
|
||||
/* Lose check, otherwise it should be 0. */
|
||||
if (global_status_register != 0x80)
|
||||
return -1;
|
||||
|
||||
return byte;
|
||||
}
|
||||
|
||||
int do_smbus_send_byte(unsigned smbus_io_base, unsigned device,
|
||||
unsigned char val)
|
||||
{
|
||||
unsigned global_status_register;
|
||||
|
||||
#if 0
|
||||
/* Not needed, upon write to PRTCL, the status will be auto-cleared. */
|
||||
if (smbus_wait_until_ready(smbus_io_base) < 0)
|
||||
return -2;
|
||||
#endif
|
||||
|
||||
outb(val, smbus_io_base + SMBHSTDAT0);
|
||||
smbus_delay();
|
||||
|
||||
/* Set the device I'm talking to. */
|
||||
outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
|
||||
smbus_delay();
|
||||
|
||||
outb(0, smbus_io_base + SMBHSTCMD);
|
||||
smbus_delay();
|
||||
|
||||
/* Set up for a byte data write. */
|
||||
outb(0x04, smbus_io_base + SMBHSTPRTCL);
|
||||
smbus_delay();
|
||||
|
||||
/* Poll for transaction completion. */
|
||||
if (smbus_wait_until_done(smbus_io_base) < 0)
|
||||
return -3;
|
||||
|
||||
/* Lose check */
|
||||
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
|
||||
|
||||
if (global_status_register != 0x80)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
|
||||
unsigned address)
|
||||
{
|
||||
unsigned char global_status_register, byte;
|
||||
|
||||
#if 0
|
||||
/* Not needed, upon write to PRTCL, the status will be auto-cleared. */
|
||||
if (smbus_wait_until_ready(smbus_io_base) < 0)
|
||||
return -2;
|
||||
#endif
|
||||
|
||||
/* Set the device I'm talking to. */
|
||||
outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
|
||||
smbus_delay();
|
||||
|
||||
/* Set the command/address. */
|
||||
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
|
||||
smbus_delay();
|
||||
|
||||
/* Byte data read */
|
||||
outb(0x07, smbus_io_base + SMBHSTPRTCL);
|
||||
smbus_delay();
|
||||
|
||||
/* Poll for transaction completion. */
|
||||
if (smbus_wait_until_done(smbus_io_base) < 0)
|
||||
return -3;
|
||||
|
||||
/* Lose check */
|
||||
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
|
||||
|
||||
/* Read results of transaction. */
|
||||
byte = inb(smbus_io_base + SMBHSTDAT0);
|
||||
|
||||
/* Lose check, otherwise it should be 0. */
|
||||
if (global_status_register != 0x80)
|
||||
return -1;
|
||||
|
||||
return byte;
|
||||
}
|
||||
|
||||
int do_smbus_write_byte(unsigned smbus_io_base, unsigned device,
|
||||
unsigned address, unsigned char val)
|
||||
{
|
||||
unsigned global_status_register;
|
||||
|
||||
#if 0
|
||||
/* Not needed, upon write to PRTCL, the status will be auto-cleared. */
|
||||
if (smbus_wait_until_ready(smbus_io_base) < 0)
|
||||
return -2;
|
||||
#endif
|
||||
|
||||
outb(val, smbus_io_base + SMBHSTDAT0);
|
||||
smbus_delay();
|
||||
|
||||
/* Set the device I'm talking to. */
|
||||
outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
|
||||
smbus_delay();
|
||||
|
||||
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
|
||||
smbus_delay();
|
||||
|
||||
/* Set up for a byte data write. */
|
||||
outb(0x06, smbus_io_base + SMBHSTPRTCL);
|
||||
smbus_delay();
|
||||
|
||||
/* Poll for transaction completion. */
|
||||
if (smbus_wait_until_done(smbus_io_base) < 0)
|
||||
return -3;
|
||||
|
||||
/* Lose check */
|
||||
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
|
||||
|
||||
if (global_status_register != 0x80)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int lsmbus_recv_byte(struct device * dev)
|
||||
{
|
||||
unsigned device;
|
||||
struct resource *res;
|
||||
struct bus *pbus;
|
||||
|
||||
device = dev->path.i2c.device;
|
||||
pbus = get_pbus_smbus(dev);
|
||||
|
||||
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
|
||||
|
||||
return do_smbus_recv_byte(res->base, device);
|
||||
}
|
||||
|
||||
int lsmbus_send_byte(struct device * dev, u8 val)
|
||||
{
|
||||
unsigned device;
|
||||
struct resource *res;
|
||||
struct bus *pbus;
|
||||
|
||||
device = dev->path.i2c.device;
|
||||
pbus = get_pbus_smbus(dev);
|
||||
|
||||
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
|
||||
|
||||
return do_smbus_send_byte(res->base, device, val);
|
||||
}
|
||||
|
||||
int lsmbus_read_byte(struct device * dev, u8 address)
|
||||
{
|
||||
unsigned device;
|
||||
struct resource *res;
|
||||
struct bus *pbus;
|
||||
|
||||
device = dev->path.i2c.device;
|
||||
pbus = get_pbus_smbus(dev);
|
||||
|
||||
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
|
||||
|
||||
return do_smbus_read_byte(res->base, device, address);
|
||||
}
|
||||
|
||||
int lsmbus_write_byte(struct device * dev, u8 address, u8 val)
|
||||
{
|
||||
unsigned device;
|
||||
struct resource *res;
|
||||
struct bus *pbus;
|
||||
|
||||
device = dev->path.i2c.device;
|
||||
pbus = get_pbus_smbus(dev);
|
||||
|
||||
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
|
||||
|
||||
return do_smbus_write_byte(res->base, device, address, val);
|
||||
}
|
||||
|
||||
struct smbus_bus_operations lops_smbus_bus = {
|
||||
.recv_byte = lsmbus_recv_byte,
|
||||
.send_byte = lsmbus_send_byte,
|
||||
.read_byte = lsmbus_read_byte,
|
||||
.write_byte = lsmbus_write_byte,
|
||||
};
|
||||
|
||||
struct device_operations ck804_smbus_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_CK804_SM}}},
|
||||
.phase3_chip_setup_dev = ck804_enable,
|
||||
.phase3_scan = scan_static_bus,
|
||||
.phase4_read_resources = pci_dev_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
.phase5_enable_resources = pci_dev_enable_resources,
|
||||
.ops_pci = &ck804_ops_pci,
|
||||
.ops_smbus_bus = &lops_smbus_bus,
|
||||
};
|
||||
|
||||
23
southbridge/nvidia/ck804/smbus.dts
Normal file
23
southbridge/nvidia/ck804/smbus.dts
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
{
|
||||
device_operations = "ck804_smbus_ops";
|
||||
};
|
||||
434
southbridge/nvidia/ck804/stage1.c
Normal file
434
southbridge/nvidia/ck804/stage1.c
Normal file
|
|
@ -0,0 +1,434 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2006 AMD
|
||||
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <mainboard.h>
|
||||
#include <console.h>
|
||||
#include <lib.h>
|
||||
#include <io.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <cpu.h>
|
||||
#include <amd/k8/k8.h>
|
||||
#include "stage1.h"
|
||||
|
||||
#ifndef CK804_NUM
|
||||
#error CK804_NUM should be defined in mainboard.h (in the mainboard directory)
|
||||
#endif
|
||||
|
||||
#define CK804_BUSN 0
|
||||
#define CK804B_BUSN 1
|
||||
|
||||
#if 0
|
||||
int set_ht_link_ck804(u8 ht_c_num)
|
||||
{
|
||||
int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val);
|
||||
unsigned vendorid = 0x10de;
|
||||
unsigned val = 0x01610169;
|
||||
/* Nvidia ck804 hardcode, hw can not set it automatically. */
|
||||
return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
|
||||
}
|
||||
#endif
|
||||
|
||||
void setup_ss_table(unsigned index, unsigned where, unsigned control,
|
||||
const u32 *register_values, int max)
|
||||
{
|
||||
int i;
|
||||
unsigned val;
|
||||
|
||||
val = inl(control);
|
||||
val &= 0xfffffffe;
|
||||
outl(val, control);
|
||||
|
||||
outl(0, index);
|
||||
|
||||
for(i = 0; i < max; i++) {
|
||||
unsigned long reg;
|
||||
reg = register_values[i];
|
||||
outl(reg, where);
|
||||
}
|
||||
|
||||
val = inl(control);
|
||||
val |= 1;
|
||||
outl(val, control);
|
||||
}
|
||||
|
||||
#define ANACTRL_IO_BASE 0x3000
|
||||
#define ANACTRL_REG_POS 0x68
|
||||
|
||||
#define SYSCTRL_IO_BASE 0x2000
|
||||
#define SYSCTRL_REG_POS 0x64
|
||||
|
||||
/*
|
||||
* 16 1 1 2 :0
|
||||
* 8 8 2 2 :1
|
||||
* 8 8 4 :2
|
||||
* 8 4 4 4 :3
|
||||
* 16 4 :4
|
||||
*/
|
||||
|
||||
#ifndef CK804_PCI_E_X
|
||||
#define CK804_PCI_E_X 4
|
||||
#endif
|
||||
|
||||
#ifndef CK804_USE_NIC
|
||||
#define CK804_USE_NIC 0
|
||||
#endif
|
||||
|
||||
#ifndef CK804_USE_ACI
|
||||
#define CK804_USE_ACI 0
|
||||
#endif
|
||||
#ifndef CK804_PCI_E_X
|
||||
#define CK804_PCI_E_X 4
|
||||
#endif
|
||||
|
||||
/*
|
||||
* We will use the offset in setup_resource_map_x_offset and
|
||||
* setup_resource_map_offset.
|
||||
*/
|
||||
#define CK804B_ANACTRL_IO_BASE 0x3000
|
||||
#define CK804B_SYSCTRL_IO_BASE 0x2000
|
||||
|
||||
#ifdef CK804B_BUSN
|
||||
#undef CK804B_BUSN
|
||||
#endif
|
||||
#define CK804B_BUSN 0x0
|
||||
|
||||
#ifndef CK804B_PCI_E_X
|
||||
#define CK804B_PCI_E_X 4
|
||||
#endif
|
||||
|
||||
#ifndef CK804_USE_NIC
|
||||
#define CK804_USE_NIC 0
|
||||
#endif
|
||||
|
||||
#ifndef CK804_USE_ACI
|
||||
#define CK804_USE_ACI 0
|
||||
#endif
|
||||
|
||||
#define CK804_CHIP_REV 3
|
||||
|
||||
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
|
||||
#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
|
||||
#else
|
||||
#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
|
||||
#endif
|
||||
|
||||
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
|
||||
#define CK804B_DEVN_BASE 1
|
||||
#else
|
||||
#define CK804B_DEVN_BASE CK804_DEVN_BASE
|
||||
#endif
|
||||
|
||||
void ck804_early_set_port(unsigned ck804_num, unsigned *busn,
|
||||
unsigned *io_base)
|
||||
{
|
||||
static const struct rmap ctrl_devport_conf[] = {
|
||||
PCM(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS, ~0x0000ff00, ANACTRL_IO_BASE),
|
||||
PCM(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS, ~0x0000ff00, SYSCTRL_IO_BASE),
|
||||
};
|
||||
|
||||
int j;
|
||||
for(j = 0; j < ck804_num; j++ ) {
|
||||
setup_resource_map_x_offset(ctrl_devport_conf,
|
||||
ARRAY_SIZE(ctrl_devport_conf),
|
||||
PCI_BDF(busn[j], 0, 0), io_base[j]);
|
||||
}
|
||||
}
|
||||
|
||||
void ck804_early_clear_port(unsigned ck804_num, unsigned *busn,
|
||||
unsigned *io_base)
|
||||
{
|
||||
static const struct rmap ctrl_devport_conf_clear[] = {
|
||||
PCM(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS, ~0x0000ff00, 0),
|
||||
PCM(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS, ~0x0000ff00, 0),
|
||||
};
|
||||
|
||||
int j;
|
||||
for(j = 0; j < ck804_num; j++ ) {
|
||||
setup_resource_map_x_offset(ctrl_devport_conf_clear,
|
||||
ARRAY_SIZE(ctrl_devport_conf_clear),
|
||||
PCI_BDF(busn[j], 0, 0) , io_base[j]);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Do early setup
|
||||
* @param ck804_num the number of ck804s on the board
|
||||
* @param busn the number of the bus the ck804 is on
|
||||
* @param io_base
|
||||
*/
|
||||
|
||||
static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
|
||||
unsigned *io_base)
|
||||
{
|
||||
static const struct rmap ctrl_conf_master[] = {
|
||||
PCM(0, CK804_DEVN_BASE + 1, 2, 0x8c, 0xffff0000, 0x00009880),
|
||||
PCM(0, CK804_DEVN_BASE + 1, 2, 0x90, 0xffff000f, 0x000074a0),
|
||||
PCM(0, CK804_DEVN_BASE + 1, 2, 0xa0, 0xfffff0ff, 0x00000a00),
|
||||
PCM(0, CK804_DEVN_BASE + 1, 2, 0xac, 0xffffff00, 0x00000000),
|
||||
|
||||
PCM(0, CK804_DEVN_BASE, 0, 0x48, 0xfffffffd, 0x00000002),
|
||||
PCM(0, CK804_DEVN_BASE, 0, 0x74, 0xfffff00f, 0x000009d0),
|
||||
PCM(0, CK804_DEVN_BASE, 0, 0x8c, 0xffff0000, 0x0000007f),
|
||||
PCM(0, CK804_DEVN_BASE, 0, 0xcc, 0xfffffff8, 0x00000003),
|
||||
PCM(0, CK804_DEVN_BASE, 0, 0xd0, 0xff000000, 0x00000000),
|
||||
PCM(0, CK804_DEVN_BASE, 0, 0xd4, 0xff000000, 0x00000000),
|
||||
PCM(0, CK804_DEVN_BASE, 0, 0xd8, 0xff000000, 0x00000000),
|
||||
PCM(0, CK804_DEVN_BASE, 0, 0xdc, 0x7f000000, 0x00000000),
|
||||
|
||||
PCM(0, CK804_DEVN_BASE + 1, 0, 0xf0, 0xfffffffd, 0x00000002),
|
||||
PCM(0, CK804_DEVN_BASE + 1, 0, 0xf8, 0xffffffcf, 0x00000010),
|
||||
|
||||
PCM(0, CK804_DEVN_BASE + 9, 0, 0x40, 0xfff8ffff, 0x00030000),
|
||||
PCM(0, CK804_DEVN_BASE + 9, 0, 0x4c, 0xfe00ffff, 0x00440000),
|
||||
PCM(0, CK804_DEVN_BASE + 9, 0, 0x74, 0xffffffc0, 0x00000000),
|
||||
|
||||
#ifdef CK804_MB_SETUP
|
||||
CK804_MB_SETUP
|
||||
#endif
|
||||
#if CK804_NUM > 1
|
||||
PCM(0, CK804_DEVN_BASE + 1, 0, 0x78, 0xc0ffffff, 0x19000000),
|
||||
PCM(0, CK804_DEVN_BASE + 1, 0, 0xe0, 0xfffffeff, 0x00000100),
|
||||
#endif
|
||||
|
||||
#if CK804_NUM == 1
|
||||
PCM(0, CK804_DEVN_BASE + 1, 0, 0x78, 0xc0ffffff, 0x19000000),
|
||||
PCM(0, CK804_DEVN_BASE + 1, 0, 0xe0, 0xfffffeff, 0x00000100),
|
||||
#endif
|
||||
|
||||
IO32(ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000),
|
||||
IO32(ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000),
|
||||
IO32(ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120),
|
||||
IO32(ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010),
|
||||
IO32(ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000),
|
||||
IO32(ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000),
|
||||
|
||||
IO32(ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008),
|
||||
IO32(ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32)),
|
||||
IO32(ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16)),
|
||||
|
||||
IO32(ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0),
|
||||
|
||||
PCM(0, CK804_DEVN_BASE + 8, 0, 0x50, ~0x1f000013, 0x15000013),
|
||||
PCM(0, CK804_DEVN_BASE + 8, 0, 0x64, ~0x00000001, 0x00000001),
|
||||
PCM(0, CK804_DEVN_BASE + 8, 0, 0x68, ~0x02000000, 0x02000000),
|
||||
PCM(0, CK804_DEVN_BASE + 8, 0, 0x70, ~0x000f0000, 0x00040000),
|
||||
PCM(0, CK804_DEVN_BASE + 8, 0, 0xa0, ~0x000001ff, 0x00000150),
|
||||
PCM(0, CK804_DEVN_BASE + 8, 0, 0xac, ~0xffff8f00, 0x02aa8b00),
|
||||
PCM(0, CK804_DEVN_BASE + 8, 0, 0x7c, ~0x00000010, 0x00000000),
|
||||
PCM(0, CK804_DEVN_BASE + 8, 0, 0xc8, ~0x0fff0fff, 0x000a000a),
|
||||
PCM(0, CK804_DEVN_BASE + 8, 0, 0xd0, ~0xf0000000, 0x00000000),
|
||||
PCM(0, CK804_DEVN_BASE + 8, 0, 0xe0, ~0xf0000000, 0x00000000),
|
||||
|
||||
IO32(ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10)),
|
||||
|
||||
// PANTA IO32(ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b),
|
||||
|
||||
IO32(ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000),
|
||||
|
||||
IO32(ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8)),
|
||||
|
||||
//SYSCTRL
|
||||
IO8(SYSCTRL_IO_BASE + 0xc0 + 8, (u8)~(0xff), (u8)((0 << 4) | (0 << 2) | (0 << 0))),
|
||||
IO8(SYSCTRL_IO_BASE + 0xc0 + 9, (u8)~(0xff), (u8)((0 << 4) | (1 << 2) | (1 << 0))),
|
||||
|
||||
#if CK804_USE_NIC == 1
|
||||
PCM(0, CK804_DEVN_BASE + 0xa, 0, 0xf8, 0xffffffbf, 0x00000040),
|
||||
|
||||
IO8(SYSCTRL_IO_BASE + 0xc0 + 19, (u8)~(0xff), (u8)((0 << 4) | (1 << 2) | (0 << 0)),
|
||||
IO8(SYSCTRL_IO_BASE + 0xc0 + 3, (u8)~(0xff), (u8)((0 << 4) | (1 << 2) | (0 << 0)),
|
||||
IO8(SYSCTRL_IO_BASE + 0xc0 + 3, (u8)~(0xff), (u8)((0 << 4) | (1 << 2) | (1 << 0)),
|
||||
PCM(0, CK804_DEVN_BASE + 1, 0, 0xe4, ~(1 << 23), (1 << 23),
|
||||
#endif
|
||||
|
||||
#if CK804_USE_ACI == 1
|
||||
IO8(SYSCTRL_IO_BASE + 0xc0 + 0x0d, (u8)~(0xff), (u8)((0 << 4) | (2 << 2) | (0 << 0)),
|
||||
IO8(SYSCTRL_IO_BASE + 0xc0 + 0x1a, (u8)~(0xff), (u8)((0 << 4) | (2 << 2) | (0 << 0)),
|
||||
#endif
|
||||
|
||||
#if CK804_NUM > 1
|
||||
IO8(SYSCTRL_IO_BASE + 0xc0 + 0, (u8)~(3 << 2), (u8)(0 << 2)),
|
||||
#endif
|
||||
};
|
||||
|
||||
static const struct rmap ctrl_conf_slave[] = {
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c, 0xffff0000, 0x00009880),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90, 0xffff000f, 0x000074a0),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0, 0xfffff0ff, 0x00000a00),
|
||||
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48, 0xfffffffd, 0x00000002),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74, 0xfffff00f, 0x000009d0),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c, 0xffff0000, 0x0000007f),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc, 0xfffffff8, 0x00000003),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0, 0xff000000, 0x00000000),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4, 0xff000000, 0x00000000),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8, 0xff000000, 0x00000000),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc, 0x7f000000, 0x00000000),
|
||||
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0, 0xfffffffd, 0x00000002),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8, 0xffffffcf, 0x00000010),
|
||||
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40, 0xfff8ffff, 0x00030000),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c, 0xfe00ffff, 0x00440000),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74, 0xffffffc0, 0x00000000),
|
||||
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78, 0xc0ffffff, 0x20000000),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0, 0xfffffeff, 0x00000000),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8, 0xffffff00, 0x000000ff),
|
||||
|
||||
IO32(CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000),
|
||||
IO32(CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000),
|
||||
IO32(CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120),
|
||||
IO32(CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010),
|
||||
IO32(CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000),
|
||||
IO32(CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000),
|
||||
|
||||
IO32(CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0),
|
||||
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50, ~0x1f000013, 0x15000013),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64, ~0x00000001, 0x00000001),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68, ~0x02000000, 0x02000000),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70, ~0x000f0000, 0x00040000),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0, ~0x000001ff, 0x00000150),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac, ~0xffff8f00, 0x02aa8b00),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c, ~0x00000010, 0x00000000),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8, ~0x0fff0fff, 0x000a000a),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0, ~0xf0000000, 0x00000000),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0, ~0xf0000000, 0x00000000),
|
||||
|
||||
IO32(CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10)),
|
||||
|
||||
//PANTA IO32(CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b),
|
||||
|
||||
IO32(CK804B_ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000),
|
||||
|
||||
IO32(CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8)),
|
||||
|
||||
#if CK804_USE_NIC == 1
|
||||
PCM(0, CK804B_DEVN_BASE + 0xa, 0, 0xf8), 0xffffffbf, 0x00000040),
|
||||
IO8(SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0))),
|
||||
IO8(SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0))),
|
||||
IO8(SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0))),
|
||||
PCM(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23)),
|
||||
#endif
|
||||
};
|
||||
|
||||
int j;
|
||||
for (j = 0; j < ck804_num; j++) {
|
||||
if (busn[j] == 0) {
|
||||
setup_resource_map_x_offset(ctrl_conf_master,
|
||||
ARRAY_SIZE(ctrl_conf_master),
|
||||
PCI_BDF(busn[0], 0, 0), io_base[0]);
|
||||
continue;
|
||||
}
|
||||
|
||||
setup_resource_map_x_offset(ctrl_conf_slave, ARRAY_SIZE(ctrl_conf_slave),
|
||||
PCI_BDF(busn[j], 0, 0), io_base[j]);
|
||||
}
|
||||
|
||||
#if 0
|
||||
for(j=0; j< ck804_num; j++) {
|
||||
/* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */
|
||||
/* SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 */
|
||||
/* CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 */
|
||||
setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40,
|
||||
io_base[j] + ANACTRL_IO_BASE+0x44,
|
||||
io_base[j] + ANACTRL_IO_BASE+0x48,
|
||||
pcie_ss_tbl, 64);
|
||||
setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0,
|
||||
io_base[j] + ANACTRL_IO_BASE+0xb4,
|
||||
io_base[j] + ANACTRL_IO_BASE+0xb8,
|
||||
sata_ss_tbl, 64);
|
||||
//PANTA setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0,
|
||||
// io_base[j] + ANACTRL_IO_BASE+0xc4,
|
||||
// io_base[j] + ANACTRL_IO_BASE+0xc8,
|
||||
// cpu_ss_tbl, 64);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef HT_CHAIN_NUM_MAX
|
||||
|
||||
#define HT_CHAIN_NUM_MAX 4
|
||||
#define HT_CHAIN_BUSN_D 0x40
|
||||
#define HT_CHAIN_IOBASE_D 0x4000
|
||||
|
||||
#endif
|
||||
|
||||
int ck804_early_setup_x(void)
|
||||
{
|
||||
unsigned busn[4], io_base[4];
|
||||
int i, ck804_num = 0;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
u32 id;
|
||||
u32 dev;
|
||||
if (i == 0) // SB chain
|
||||
dev = PCI_BDF(i * 0x40, CK804_DEVN_BASE, 0);
|
||||
else
|
||||
dev = PCI_BDF(i * 0x40, CK804B_DEVN_BASE, 0);
|
||||
id = pci_conf1_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (id == 0x005e10de) {
|
||||
busn[ck804_num] = i * 0x40;
|
||||
io_base[ck804_num] = i * 0x4000;
|
||||
ck804_num++;
|
||||
}
|
||||
}
|
||||
|
||||
ck804_early_set_port(ck804_num, busn, io_base);
|
||||
ck804_early_setup(ck804_num, busn, io_base);
|
||||
ck804_early_clear_port(ck804_num, busn, io_base);
|
||||
|
||||
//return set_ht_link_ck804(4);
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int get_sbdn(unsigned int bus)
|
||||
{
|
||||
return CK804_DEVN_BASE;
|
||||
}
|
||||
|
||||
void set_bios_reset(void);
|
||||
void hard_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
|
||||
/* full reset */
|
||||
outb(0x0a, 0x0cf9);
|
||||
outb(0x0e, 0x0cf9);
|
||||
}
|
||||
|
||||
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
|
||||
{
|
||||
/* default value for ck804 is good */
|
||||
}
|
||||
|
||||
void soft_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
/* link reset */
|
||||
outb(0x02, 0x0cf9);
|
||||
outb(0x06, 0x0cf9);
|
||||
}
|
||||
|
||||
void soft_reset_x(unsigned sbbusn, unsigned sbdn)
|
||||
{
|
||||
soft_reset();
|
||||
}
|
||||
205
southbridge/nvidia/ck804/stage1.h
Normal file
205
southbridge/nvidia/ck804/stage1.h
Normal file
|
|
@ -0,0 +1,205 @@
|
|||
/*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
*/
|
||||
|
||||
static const u32 pcie_ss_tbl[] = {
|
||||
0x0C504103f,
|
||||
0x0C504103f,
|
||||
0x0C504103f,
|
||||
0x0C5042040,
|
||||
0x0C5042040,
|
||||
0x0C5042040,
|
||||
0x0C5043041,
|
||||
0x0C5043041,
|
||||
0x0C5043041,
|
||||
0x0C5043041,
|
||||
0x0C5044042,
|
||||
0x0C5044042,
|
||||
0x0C5044042,
|
||||
0x0C5045043,
|
||||
0x0C5045043,
|
||||
0x0C5045043,
|
||||
0x0C5045043,
|
||||
0x0C5045043,
|
||||
0x0C5046044,
|
||||
0x0C5046044,
|
||||
0x0C5046044,
|
||||
0x0C5046044,
|
||||
0x0C5047045,
|
||||
0x0C5047045,
|
||||
0x0C5047045,
|
||||
0x0C5047045,
|
||||
0x0C5047045,
|
||||
0x0C5048046,
|
||||
0x0C5048046,
|
||||
0x0C5048046,
|
||||
0x0C5048046,
|
||||
0x0C5049047,
|
||||
0x0C5049047,
|
||||
0x0C5049047,
|
||||
0x0C504a048,
|
||||
0x0C504a048,
|
||||
0x0C504b049,
|
||||
0x0C504b049,
|
||||
0x0C504a048,
|
||||
0x0C504a048,
|
||||
0x0C5049047,
|
||||
0x0C5049047,
|
||||
0x0C5048046,
|
||||
0x0C5048046,
|
||||
0x0C5048046,
|
||||
0x0C5047045,
|
||||
0x0C5047045,
|
||||
0x0C5047045,
|
||||
0x0C5047045,
|
||||
0x0C5047045,
|
||||
0x0C5046044,
|
||||
0x0C5046044,
|
||||
0x0C5046044,
|
||||
0x0C5046044,
|
||||
0x0C5045043,
|
||||
0x0C5045043,
|
||||
0x0C5045043,
|
||||
0x0C5044042,
|
||||
0x0C5044042,
|
||||
0x0C5044042,
|
||||
0x0C5043041,
|
||||
0x0C5043041,
|
||||
0x0C5042040,
|
||||
0x0C5042040,
|
||||
};
|
||||
|
||||
static const u32 sata_ss_tbl[] = {
|
||||
0x0c9044042,
|
||||
0x0c9044042,
|
||||
0x0c9044042,
|
||||
0x0c9045043,
|
||||
0x0c9045043,
|
||||
0x0c9045043,
|
||||
0x0c9045043,
|
||||
0x0c9045043,
|
||||
0x0c9046044,
|
||||
0x0c9046044,
|
||||
0x0c9046044,
|
||||
0x0c9046044,
|
||||
0x0c9047045,
|
||||
0x0c9047045,
|
||||
0x0c9047045,
|
||||
0x0c9047045,
|
||||
0x0c9047045,
|
||||
0x0c9048046,
|
||||
0x0c9048046,
|
||||
0x0c9048046,
|
||||
0x0c9048046,
|
||||
0x0c9049047,
|
||||
0x0c9049047,
|
||||
0x0c9049047,
|
||||
0x0c9049047,
|
||||
0x0c904a048,
|
||||
0x0c904a048,
|
||||
0x0c904a048,
|
||||
0x0c904a048,
|
||||
0x0c904b049,
|
||||
0x0c904b049,
|
||||
0x0c904b049,
|
||||
0x0c904b049,
|
||||
0x0c904b049,
|
||||
0x0c904b049,
|
||||
0x0c904a048,
|
||||
0x0c904a048,
|
||||
0x0c904a048,
|
||||
0x0c904a048,
|
||||
0x0c9049047,
|
||||
0x0c9049047,
|
||||
0x0c9049047,
|
||||
0x0c9049047,
|
||||
0x0c9048046,
|
||||
0x0c9048046,
|
||||
0x0c9048046,
|
||||
0x0c9048046,
|
||||
0x0c9047045,
|
||||
0x0c9047045,
|
||||
0x0c9047045,
|
||||
0x0c9047045,
|
||||
0x0c9047045,
|
||||
0x0c9046044,
|
||||
0x0c9046044,
|
||||
0x0c9046044,
|
||||
0x0c9046044,
|
||||
0x0c9045043,
|
||||
0x0c9045043,
|
||||
0x0c9045043,
|
||||
0x0c9045043,
|
||||
0x0c9045043,
|
||||
0x0c9044042,
|
||||
0x0c9044042,
|
||||
0x0c9044042,
|
||||
};
|
||||
|
||||
static const u32 cpu_ss_tbl[] = {
|
||||
0x0C5038036,
|
||||
0x0C5038036,
|
||||
0x0C5038036,
|
||||
0x0C5037035,
|
||||
0x0C5037035,
|
||||
0x0C5037035,
|
||||
0x0C5037035,
|
||||
0x0C5036034,
|
||||
0x0C5036034,
|
||||
0x0C5036034,
|
||||
0x0C5036034,
|
||||
0x0C5036034,
|
||||
0x0C5035033,
|
||||
0x0C5035033,
|
||||
0x0C5035033,
|
||||
0x0C5035033,
|
||||
0x0C5035033,
|
||||
0x0C5035033,
|
||||
0x0C5034032,
|
||||
0x0C5034032,
|
||||
0x0C5034032,
|
||||
0x0C5034032,
|
||||
0x0C5034032,
|
||||
0x0C5034032,
|
||||
0x0C5035033,
|
||||
0x0C5035033,
|
||||
0x0C5035033,
|
||||
0x0C5035033,
|
||||
0x0C5035033,
|
||||
0x0C5036034,
|
||||
0x0C5036034,
|
||||
0x0C5036034,
|
||||
0x0C5036034,
|
||||
0x0C5036034,
|
||||
0x0C5037035,
|
||||
0x0C5037035,
|
||||
0x0C5037035,
|
||||
0x0C5037035,
|
||||
0x0C5038036,
|
||||
0x0C5038036,
|
||||
0x0C5038036,
|
||||
0x0C5038036,
|
||||
0x0C5039037,
|
||||
0x0C5039037,
|
||||
0x0C5039037,
|
||||
0x0C5039037,
|
||||
0x0C503a038,
|
||||
0x0C503a038,
|
||||
0x0C503a038,
|
||||
0x0C503a038,
|
||||
0x0C503b039,
|
||||
0x0C503b039,
|
||||
0x0C503b039,
|
||||
0x0C503b039,
|
||||
0x0C503b039,
|
||||
0x0C503a038,
|
||||
0x0C503a038,
|
||||
0x0C503a038,
|
||||
0x0C503a038,
|
||||
0x0C503a038,
|
||||
0x0C5039037,
|
||||
0x0C5039037,
|
||||
0x0C5039037,
|
||||
0x0C5039037,
|
||||
};
|
||||
29
southbridge/nvidia/ck804/stage1_enable_rom.c
Normal file
29
southbridge/nvidia/ck804/stage1_enable_rom.c
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
*/
|
||||
|
||||
#include <mainboard.h>
|
||||
#include <types.h>
|
||||
#include <device/pci.h>
|
||||
|
||||
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
|
||||
#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
|
||||
#else
|
||||
#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
|
||||
#endif
|
||||
|
||||
void ck804_enable_rom(void)
|
||||
{
|
||||
unsigned char byte;
|
||||
u32 addr;
|
||||
|
||||
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
|
||||
/* Locate the ck804 LPC. */
|
||||
addr = PCI_BDEVFN(0, PCI_DEVFN((CK804_DEVN_BASE + 1), 0));
|
||||
|
||||
/* Set the 4MB enable bit. */
|
||||
byte = pci_conf1_read_config8(addr, 0x88);
|
||||
byte |= 0x80;
|
||||
pci_conf1_write_config8(addr, 0x88, byte);
|
||||
}
|
||||
55
southbridge/nvidia/ck804/stage1_smbus.c
Normal file
55
southbridge/nvidia/ck804/stage1_smbus.c
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* AMD 8111 "southbridge"
|
||||
* This file is part of the coreboot project.
|
||||
* Copyright 2004 Tyan Computer
|
||||
* (Written by Yinghai Lu <yhlu@tyan.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
|
||||
*/
|
||||
#include <types.h>
|
||||
#include <console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "ck804_smbus.h"
|
||||
|
||||
#define SMBUS_IO_BASE 0x1000
|
||||
|
||||
void enable_smbus(void)
|
||||
{
|
||||
u32 dev;
|
||||
|
||||
if (!pci_conf1_find_on_bus(0, PCI_VENDOR_ID_NVIDIA, 0x0052, &dev))
|
||||
die("SMBus controller not found\n");
|
||||
|
||||
printk(BIOS_DEBUG,"SMBus controller enabled\n");
|
||||
|
||||
/* Set SMBus I/O base. */
|
||||
pci_conf1_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
|
||||
|
||||
/* Set SMBus I/O space enable. */
|
||||
pci_conf1_write_config16(dev, 0x4, 0x01);
|
||||
|
||||
/* Clear any lingering errors, so the transaction will run. */
|
||||
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
}
|
||||
|
||||
int smbus_read_byte(u16 dev, u16 address)
|
||||
{
|
||||
return do_smbus_read_byte(SMBUS_IO_BASE, dev, address);
|
||||
}
|
||||
|
||||
int smbus_write_byte(u16 dev, u16 address, u8 val)
|
||||
{
|
||||
return do_smbus_write_byte(SMBUS_IO_BASE, dev, address, val);
|
||||
}
|
||||
62
southbridge/nvidia/ck804/usb.c
Normal file
62
southbridge/nvidia/ck804/usb.c
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <statictree.h>
|
||||
#include "ck804.h"
|
||||
|
||||
static void usb1_init(struct device *dev)
|
||||
{
|
||||
struct southbridge_nvidia_ck804_usb_config const *conf = dev->device_configuration;
|
||||
if (conf->usb1_hc_reset) {
|
||||
/*
|
||||
* Somehow the warm reset does not really reset the USB
|
||||
* controller. Later, during boot, when the Bus Master bit is
|
||||
* set, the USB controller trashes the memory, causing weird
|
||||
* misbehavior. Was detected on Sun Ultra40, where mptable
|
||||
* was damaged.
|
||||
*/
|
||||
u32 bar0 = pci_read_config32(dev, 0x10);
|
||||
u32 *regs = (u32 *) (bar0 & ~0xfff);
|
||||
|
||||
/* OHCI USB HCCommandStatus Register, HostControllerReset bit */
|
||||
regs[2] |= 1;
|
||||
}
|
||||
}
|
||||
|
||||
struct device_operations ck804_usb_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_CK804_USB}}},
|
||||
.phase3_chip_setup_dev = ck804_enable,
|
||||
.phase3_scan = NULL,
|
||||
.phase4_read_resources = pci_dev_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
.phase5_enable_resources = pci_dev_enable_resources,
|
||||
.phase6_init = usb1_init,
|
||||
.ops_pci = &ck804_ops_pci,
|
||||
};
|
||||
|
||||
24
southbridge/nvidia/ck804/usb.dts
Normal file
24
southbridge/nvidia/ck804/usb.dts
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
{
|
||||
device_operations = "ck804_usb2_ops";
|
||||
usb1_hc_reset = "1";
|
||||
};
|
||||
50
southbridge/nvidia/ck804/usb2.c
Normal file
50
southbridge/nvidia/ck804/usb2.c
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "ck804.h"
|
||||
|
||||
static void usb2_init(struct device *dev)
|
||||
{
|
||||
u32 dword;
|
||||
dword = pci_read_config32(dev, 0xf8);
|
||||
dword |= 40;
|
||||
pci_write_config32(dev, 0xf8, dword);
|
||||
}
|
||||
|
||||
struct device_operations ck804_usb2_ops = {
|
||||
.id = {.type = DEVICE_ID_PCI,
|
||||
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_DEVICE_ID_NVIDIA_CK804_USB2}}},
|
||||
.phase3_chip_setup_dev = ck804_enable,
|
||||
.phase3_scan = NULL,
|
||||
.phase4_read_resources = pci_dev_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
.phase5_enable_resources = pci_dev_enable_resources,
|
||||
.phase6_init = usb2_init,
|
||||
.ops_pci = &ck804_ops_pci,
|
||||
};
|
||||
|
||||
23
southbridge/nvidia/ck804/usb2.dts
Normal file
23
southbridge/nvidia/ck804/usb2.dts
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
{
|
||||
device_operations = "ck804_usb_ops";
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue