mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
This patch fixes a few small problems and gets cn700 to read from an IDE
disk and attempt to boot a linux kernel. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1087 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
parent
54f58ebae7
commit
305d400a83
11 changed files with 97 additions and 158 deletions
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@ -89,7 +89,7 @@ static void set_c7_speed(int model) {
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(int)((msr.lo >> 8) & 0xff),
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(int)((msr.hi >> 24) & 0xff), (int)((msr.hi >> 8) & 0xff));
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printk(BIOS_DEBUG, " msr.lo = %x\n", msr.lo);
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printk(BIOS_DEBUG, " msr.lo = %x, msr.hi = %x\n", msr.lo, msr.hi);
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/* Wait while CPU is busy */
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cnt = 0;
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@ -109,7 +109,7 @@ static void set_c7_speed(int model) {
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new = current;
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switch (model) {
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case 10: // model A
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for (i = 0; i < ARRAY_SIZE(c7a_speed_translation); i += 2) {
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for (i = 0; i <= ARRAY_SIZE(c7a_speed_translation); i += 2) {
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if ((c7a_speed_translation[i] == current) &&
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((c7a_speed_translation[i + 1] & 0xff00) ==
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(msr.hi & 0xff00))) {
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@ -118,7 +118,7 @@ static void set_c7_speed(int model) {
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}
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break;
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case 13: // model D
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for (i = 0; i < ARRAY_SIZE(c7d_speed_translation); i += 2) {
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for (i = 0; i <= ARRAY_SIZE(c7d_speed_translation); i += 2) {
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if ((c7d_speed_translation[i] == current) &&
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((c7d_speed_translation[i + 1] & 0xff00) ==
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(msr.hi & 0xff00))) {
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@ -203,8 +203,8 @@ static void c7_init(struct device * dev)
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/* Set up Memory Type Range Registers */
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//these don't exist yet
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//x86_setup_mtrrs(36);
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//x86_mtrr_check();
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x86_setup_mtrrs(36);
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x86_mtrr_check();
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/* Enable the local cpu apics */
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//setup_lapic();
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@ -28,6 +28,7 @@ config BOARD_JETWAY_J7F2
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select NORTHBRIDGE_VIA_CN700
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select SOUTHBRIDGE_VIA_VT8237
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select SUPERIO_FINTEK_F71805F
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select PIRQ_TABLE
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help
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Jetway J7F2-Series board.
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endchoice
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@ -43,8 +43,8 @@
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/{
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mainboard_vendor = "Jetway";
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mainboard_name = "J7F2";
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mainboard_pci_subsystem_vendor = "0xdead"; /* TODO */
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mainboard_pci_subsystem_device = "0xbeef"; /* TODO */
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subsystem_vendor = "0xdead"; /* TODO */
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subsystem_device = "0xbeef"; /* TODO */
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cpus {
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/config/("arch/x86/via/c7.dts");
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};
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@ -66,23 +66,33 @@
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/* How do I represent the bus and pci devices hanging here? */
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pci@1,0 {
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/config/("northbridge/via/cn700/pci.dts");
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pci@0,1 {
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pci@0,0 {
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/config/("northbridge/via/cn700/vga.dts");
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};
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};
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pci@f,0 {};
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pci@10,0 {
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pci@f,0 {
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/config/("southbridge/via/vt8237/sata.dts");
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};
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pci@10,1 {
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pci@f,1 {
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/config/("southbridge/via/vt8237/ide.dts");
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ide0_enable = "1";
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ide1_enable = "0";
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ide0_80pin_cable = "1";
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ide1_80pin_cable = "0";
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};
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pci@10,0 { };
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pci@10,1 { };
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pci@10,2 { };
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pci@10,3 { };
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pci@10,4 { };
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pci@11,0 {
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/config/("southbridge/via/vt8237/lpc.dts");
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ioport@4e {
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/config/("superio/fintek/f71805f/dts");
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com2enable = "1";
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};
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};
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ioport@4e {
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/config/("superio/fintek/f71805f/dts");
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com2enable = "1";
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};
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pci@11,5 { };
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pci@12,0 { };
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};
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};
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@ -34,12 +34,12 @@ void sdram_set_spd_registers(struct board_info *);
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void ddr2_sdram_enable(struct board_info *);
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/* VGA stuff */
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#define SR_INDEX 0x3c4
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#define SR_DATA 0x3c5
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#define CRTM_INDEX 0x3b4
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#define CRTM_DATA 0x3b5
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#define CRTC_INDEX 0x3d4
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#define CRTC_DATA 0x3d5
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#define SR_INDEX 0x3c4
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#define SR_DATA 0x3c5
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#define CRTM_INDEX 0x3b4
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#define CRTM_DATA 0x3b5
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#define CRTC_INDEX 0x3d4
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#define CRTC_DATA 0x3d5
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/* Memory Controller Registers */
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#define RANK0_END 0x40
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@ -232,11 +232,11 @@ void sdram_set_registers(struct board_info *dev)
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* TODO: #if and option in Kconfig
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*/
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/* Set WR=5 and RFC */
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//pci_conf1_write_config8(dev->d0f3, 0x61, 0x94);
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pci_conf1_write_config8(dev->d0f3, 0x61, 0x94);
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/* Set CAS=5 */
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//pci_conf1_write_config8(dev->d0f3, 0x62, 0x7a);
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//pci_conf1_write_config8(dev->d0f3, 0x63, 0x00);
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//pci_conf1_write_config8(dev->d0f3, 0x64, 0x88);
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pci_conf1_write_config8(dev->d0f3, 0x62, 0x7a);
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pci_conf1_write_config8(dev->d0f3, 0x63, 0x00);
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pci_conf1_write_config8(dev->d0f3, 0x64, 0x88);
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/* Set to DDR2 sdram, BL=8 (0xc8, 0xc0 for BL=4) */
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pci_conf1_write_config8(dev->d0f3, 0x6c, 0xc8);
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@ -404,7 +404,7 @@ static void do_tras_cas(struct board_info *dev, int i, int ram_cycle)
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spd_data = check_timing(spd_data, 5, 20);
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reg8 = pci_conf1_read_config8(dev->d0f3, 0x62);
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if ((spd_data - 10) > (reg8 >> 4))
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if ((spd_data - 5) > (reg8 >> 4))
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{
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reg8 &= 0x0f;
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reg8 |= ((spd_data -10) << 4);
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@ -86,7 +86,7 @@ static void cn700_pci_domain_set_resources(struct device *dev)
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pci_tolm = find_pci_tolm(&dev->link[0]);
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mc_dev = dev_find_pci_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
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/*
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* Once the register value is not zero, the RAM size is
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@ -108,11 +108,12 @@ static void cn700_pci_domain_set_resources(struct device *dev)
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}
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/* Report the memory regions. */
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idx = 10;
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/* TODO: Hole needed? */
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ram_resource(dev, idx++, 0, 640); /* First 640k */
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ram_resource(dev, idx++, 0, 640);
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/* Leave a hole for VGA, 0xa0000 - 0xc0000 */
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ram_resource(dev, idx++, 768,
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(tolmk - 768 - (CONFIG_CN700_VIDEO_MB * 1024)));
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/* TODO: shadow ram needs to be controlled via dts */
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ram_resource(dev, idx++, 1024,
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(tolmk - 1024 - (CONFIG_CN700_VIDEO_MB * 1024)));
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phase4_assign_resources(&dev->link[0]);
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}
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@ -129,5 +130,3 @@ struct device_operations cn700_north_domain = {
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.phase6_init = 0,
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.ops_pci_bus = &pci_cf8_conf1,
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};
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@ -24,59 +24,6 @@
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#include <config.h>
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#include "cn700.h"
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static void enable_shadow_ram(void)
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{
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u8 shadowreg;
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printk(BIOS_DEBUG, "Enabling shadow ram\n");
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/* Enable shadow ram as normal dram */
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/* 0xc0000-0xcffff */
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pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff);
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/* 0xd0000-0xdffff */
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pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff);
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/* 0xe0000-0xeffff */
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pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff);
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/* 0xf0000-0xfffff */
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shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83);
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shadowreg |= 0x30;
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pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg);
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/* Do it again for the vlink controller */
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shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63);
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shadowreg |= 0x30;
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg);
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}
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static void enable_vlink(void)
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{
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printk(BIOS_DEBUG, "Enabling Via V-Link\n");
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04);
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//pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98);
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77);
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/* This has to be done last, I think */
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pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
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}
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/**
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* Configure the bus between the cpu and the northbridge. This might be able to
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* be moved to post-ram code in the future. For the most part, these registers
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@ -92,6 +39,7 @@ static void enable_vlink(void)
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static void c7_cpu_setup(void)
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{
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u32 dev = PCI_BDF(0, 0, 2);
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u8 reg8;
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/* Host bus interface registers (D0F2 0x50-0x67) */
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/* Request phase control */
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@ -114,6 +62,13 @@ static void c7_cpu_setup(void)
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* 110/111 : Reserved
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* bits 4:0: Reserved
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*/
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reg8 = pci_conf1_read_config8(dev, 0x57);
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reg8 &= (0x7 << 5);
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//reg8 |= (0x4 << 5);
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reg8 |= (0x3 << 5);
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pci_conf1_write_config8(dev, 0x57, reg8);
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/* CPU Miscellaneous Control */
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pci_conf1_write_config8(dev, 0x59, 0x44);
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/* Write Policy */
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@ -179,7 +134,5 @@ void cn700_stage1(void)
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pci_conf1_write_config8(PCI_BDF(0, 1, 0), 0x19, 0x1);
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pci_conf1_write_config8(PCI_BDF(0, 1, 0), 0x1a, 0x1);
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enable_shadow_ram();
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enable_vlink();
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c7_cpu_setup();
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}
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@ -25,4 +25,9 @@ STAGE2_CHIPSET_SRC += $(src)/southbridge/via/vt8237/vt8237.c \
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$(src)/southbridge/via/vt8237/ide.c \
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$(src)/southbridge/via/vt8237/sata.c
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ifeq ($(CONFIG_PIRQ_TABLE),y)
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STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82801gx/irq_tables.c
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endif
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endif
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@ -230,44 +230,34 @@ static void vt8237_common_init(struct device *dev)
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{
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u8 enables, byte;
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/* Enable the RTC. */
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byte = pci_read_config8(dev, 0x51);
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byte |= (1 << 3);
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pci_write_config8(dev, 0x51, byte);
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/* Enable addr/data stepping. */
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byte = pci_read_config8(dev, PCI_COMMAND);
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byte |= PCI_COMMAND_WAIT;
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pci_write_config8(dev, PCI_COMMAND, byte);
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/* Enable the internal I/O decode. */
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enables = pci_read_config8(dev, 0x6C);
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enables |= 0x80;
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pci_write_config8(dev, 0x6C, enables);
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/*
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* ROM decode
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* bit range
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* 7 000E0000h-000EFFFFh
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* 6 FFF00000h-FFF7FFFFh
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* 5 FFE80000h-FFEFFFFFh
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* 4 FFE00000h-FFE7FFFFh
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* 3 FFD80000h-FFDFFFFFh
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* 2 FFD00000h-FFD7FFFFh
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* 1 FFC80000h-FFCFFFFFh
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* 0 FFC00000h-FFC7FFFFh
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* So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte.
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*/
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pci_write_config8(dev, 0x41, 0x7f);
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byte = pci_read_config8(dev, 0x6C);
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byte |= 0x80;
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pci_write_config8(dev, 0x6C, byte);
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/*
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* Set bit 6 of 0x40 (I/O recovery time).
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* IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so
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* that PCI interrupts can be properly marked as level triggered.
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*/
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enables = pci_read_config8(dev, 0x40);
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enables |= 0x44;
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pci_write_config8(dev, 0x40, enables);
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byte = pci_read_config8(dev, 0x40);
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byte |= 0x44;
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pci_write_config8(dev, 0x40, byte);
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/* Line buffer control */
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enables = pci_read_config8(dev, 0x42);
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enables |= 0xf8;
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pci_write_config8(dev, 0x42, enables);
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byte = pci_read_config8(dev, 0x42);
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byte |= 0xf8;
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pci_write_config8(dev, 0x42, byte);
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/* Delay transaction control */
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pci_write_config8(dev, 0x43, 0xb);
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@ -294,16 +284,14 @@ static void vt8237_common_init(struct device *dev)
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/* Enable serial IRQ, 6PCI clocks. */
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pci_write_config8(dev, 0x52, 0x9);
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/* Power management setup */
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/* Power Management setup. */
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setup_pm(dev);
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/* Enable the RTC. */
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enables = pci_read_config8(dev, 0x51);
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enables |= (1 << 3);
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pci_write_config8(dev, 0x51, enables);
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/* Start the RTC. */
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rtc_init(0);
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/* Initialize ISA DMA. */
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isa_dma_init();
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}
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static void vt8237_read_resources(struct device *dev)
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@ -314,6 +302,8 @@ static void vt8237_read_resources(struct device *dev)
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struct resource *res;
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pci_dev_read_resources(dev);
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#ifdef VT8237_APIC_FIXED
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/* Fixed APIC resource */
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res = new_resource(dev, 0x44);
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/* Possible breakage */
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@ -324,6 +314,7 @@ static void vt8237_read_resources(struct device *dev)
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res->gran = 8;
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res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
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IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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#endif
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}
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/**
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@ -342,10 +333,10 @@ static void init_keyboard(struct device *dev)
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struct southbridge_via_vt8237_lpc_config *sb =
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(struct southbridge_via_vt8237_lpc_config *)dev->device_configuration;
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u8 regval;
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if (sb->enable_keyboard)
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{
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u8 regval;
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/* Enable PS/2 mouse, Keyboard, and KBC Config */
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regval = pci_read_config8(dev, 0x51);
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regval |= (1 << 2)|(1 << 1)|1;
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@ -359,7 +350,7 @@ static void southbridge_init_common(struct device *dev)
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{
|
||||
vt8237_common_init(dev);
|
||||
pci_routing_fixup(dev);
|
||||
setup_ioapic(dev);
|
||||
//setup_ioapic(dev);
|
||||
setup_i8259();
|
||||
init_keyboard(dev);
|
||||
}
|
||||
|
@ -448,7 +439,7 @@ struct device_operations vt8237r_lpc = {
|
|||
{.pci = {.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = PCI_DEVICE_ID_VIA_VT8237R_LPC}}},
|
||||
.constructor = default_device_constructor,
|
||||
.phase3_chip_setup_dev = vt8237r_init,
|
||||
//.phase3_chip_setup_dev = vt8237r_init,
|
||||
.phase3_scan = scan_static_bus,
|
||||
.phase4_read_resources = vt8237_read_resources,
|
||||
.phase4_set_resources = pci_set_resources,
|
||||
|
|
|
@ -155,8 +155,9 @@ u8 smbus_read_byte(u16 dimm, u8 offset, u16 smbus_io_base)
|
|||
*/
|
||||
void enable_smbus(u16 smbus_io_base)
|
||||
{
|
||||
u32 dev;
|
||||
u32 dev = PCI_BDF(0, 17, 0);
|
||||
|
||||
#if 0
|
||||
/* Power management controller */
|
||||
pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC,
|
||||
&dev);
|
||||
|
@ -178,6 +179,7 @@ void enable_smbus(u16 smbus_io_base)
|
|||
printk(BIOS_DEBUG, "VT8237R Power management controller found "
|
||||
"at 0x%x\n", dev);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* 7 = SMBus Clock from RTC 32.768KHz
|
||||
* 5 = Internal PLL reset from susp
|
||||
|
@ -201,37 +203,15 @@ void enable_smbus(u16 smbus_io_base)
|
|||
inb(smbus_io_base + SMBHSTCTL);
|
||||
}
|
||||
|
||||
/* The change from RAID to SATA in phase6 causes coreboot to lock up, so do it
|
||||
* as early as possible. Move back to stage2 later */
|
||||
static void sata_stage1(void)
|
||||
{
|
||||
u32 dev;
|
||||
u8 reg;
|
||||
|
||||
pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_SATA, &dev);
|
||||
|
||||
printk(BIOS_DEBUG, "Configuring VIA SATA controller\n");
|
||||
|
||||
/* Class IDE Disk */
|
||||
reg = pci_conf1_read_config8(dev, SATA_MISC_CTRL);
|
||||
reg &= 0x7f; /* Sub Class Write Protect off */
|
||||
pci_conf1_write_config8(dev, SATA_MISC_CTRL, reg);
|
||||
|
||||
/* Change the device class to SATA from RAID. */
|
||||
pci_conf1_write_config8(dev, PCI_CLASS_DEVICE, 0x1);
|
||||
reg |= 0x80; /* Sub Class Write Protect on */
|
||||
pci_conf1_write_config8(dev, SATA_MISC_CTRL, reg);
|
||||
}
|
||||
|
||||
void vt8237_stage1(u16 smbus_io_base)
|
||||
{
|
||||
u32 dev;
|
||||
u32 ide_dev;
|
||||
u32 dev = PCI_BDF(0, 17, 0);
|
||||
//u32 ide_dev;
|
||||
|
||||
printk(BIOS_DEBUG, "Doing vt8237r/s stage1 init\n");
|
||||
|
||||
pci_conf1_find_device(0x1106, 0x3227, &dev);
|
||||
pci_conf1_find_device(0x1106, 0x0571, &ide_dev);
|
||||
//pci_conf1_find_device(0x1106, 0x3227, &dev);
|
||||
//pci_conf1_find_device(0x1106, 0x0571, &ide_dev);
|
||||
|
||||
/* Disable GP3 timer, or else the system reboots when it runs out.
|
||||
* Datasheets say this is disabled by default, they're wrong. */
|
||||
|
@ -248,12 +228,12 @@ void vt8237_stage1(u16 smbus_io_base)
|
|||
|
||||
pci_conf1_write_config8(dev, 0x50, 0x80);//disable mc97
|
||||
pci_conf1_write_config8(dev, 0x51, 0x1f);
|
||||
pci_conf1_write_config8(dev, 0x58, 0x60);
|
||||
pci_conf1_write_config8(dev, 0x59, 0x80);
|
||||
pci_conf1_write_config8(dev, 0x5b, 0x08);
|
||||
//pci_conf1_write_config8(dev, 0x58, 0x60);
|
||||
//pci_conf1_write_config8(dev, 0x59, 0x80);
|
||||
//pci_conf1_write_config8(dev, 0x5b, 0x08);
|
||||
|
||||
/* Make it respond to IO space */
|
||||
pci_conf1_write_config8(ide_dev, 0x04, 0x07);
|
||||
//pci_conf1_write_config8(ide_dev, 0x04, 0x07);
|
||||
|
||||
/* Compatibility mode addresses */
|
||||
//pci_conf1_write_config32(ide_dev, 0x10, 0);
|
||||
|
@ -264,9 +244,9 @@ void vt8237_stage1(u16 smbus_io_base)
|
|||
/* Native mode base address */
|
||||
//pci_conf1_write_config32(ide_dev, 0x20, BUS_MASTER_ADDR | 1);
|
||||
|
||||
pci_conf1_write_config8(ide_dev, 0x40, 0x3);//was 0x3
|
||||
pci_conf1_write_config8(ide_dev, 0x41, 0xf2);
|
||||
pci_conf1_write_config8(ide_dev, 0x42, 0x09);
|
||||
//pci_conf1_write_config8(ide_dev, 0x40, 0x3);//was 0x3
|
||||
//pci_conf1_write_config8(ide_dev, 0x41, 0xf2);
|
||||
//pci_conf1_write_config8(ide_dev, 0x42, 0x09);
|
||||
|
||||
//sata_stage1();
|
||||
enable_smbus(smbus_io_base);
|
||||
|
|
|
@ -38,14 +38,14 @@ void vt8237_enable(struct device *dev)
|
|||
const u8 func = dev->path.pci.devfn & 0x7;
|
||||
const u8 device = dev->path.pci.devfn >> 3;
|
||||
const int d16_index[6] = {12, 13, 10, 8, 9, 7};
|
||||
|
||||
|
||||
|
||||
printk(BIOS_DEBUG, "Enabling/Disabling device 0x%x function 0x%x.\n",
|
||||
device, func);
|
||||
|
||||
if(dev->id.pci.vendor != PCI_VENDOR_ID_VIA)
|
||||
return;
|
||||
|
||||
|
||||
lpc_dev = dev_find_slot(0, PCI_BDF(0, 17, 0));
|
||||
sb_fn_ctrl = pci_read_config8(lpc_dev, 0x50) << 8;
|
||||
sb_fn_ctrl |= pci_read_config8(lpc_dev, 0x51);
|
||||
|
|
Loading…
Add table
Reference in a new issue