mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Start of Artec Group ThinCan DBE63 support.
* Copying of files from other mainboards as a starting point: amd/db800/Makefile artecgroup/dbe62/cmos.layout artecgroup/dbe62/dts amd/db800/initram.c artecgroup/dbe61/irq_tables.h artecgroup/dbe62/stage1 * Kconfig integration. Behind CONFIG_EXPERIMENTAL for now, as the board is not in the market yet. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1119 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Mart Raudsepp
parent
f41147ac3e
commit
cc9707120e
7 changed files with 449 additions and 0 deletions
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@ -43,6 +43,17 @@ config BOARD_ARTECGROUP_DBE62
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help
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Artec Group DBE62 ThinCan.
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config BOARD_ARTECGROUP_DBE63
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bool "DBE63"
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select ARCH_X86
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select CPU_AMD_GEODELX
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select NORTHBRIDGE_AMD_GEODELX
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select SOUTHBRIDGE_AMD_CS5536
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select PIRQ_TABLE
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depends EXPERIMENTAL
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help
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Artec Group DBE63 ThinCan.
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endchoice
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config MAINBOARD_DIR
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@ -54,3 +65,8 @@ config MAINBOARD_DIR
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string
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default artecgroup/dbe62
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depends BOARD_ARTECGROUP_DBE62
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config MAINBOARD_DIR
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string
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default artecgroup/dbe63
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depends BOARD_ARTECGROUP_DBE63
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34
mainboard/artecgroup/dbe63/Makefile
Normal file
34
mainboard/artecgroup/dbe63/Makefile
Normal file
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@ -0,0 +1,34 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2006-2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
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INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
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$(src)/northbridge/amd/geodelx/raminit.c \
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$(src)/southbridge/amd/cs5536/smbus_initram.c \
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$(src)/arch/x86/geodelx/geodelx.c
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STAGE2_MAINBOARD_SRC =
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$(obj)/coreboot.vpd:
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$(Q)printf " BUILD DUMMY VPD\n"
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$(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
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74
mainboard/artecgroup/dbe63/cmos.layout
Normal file
74
mainboard/artecgroup/dbe63/cmos.layout
Normal file
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@ -0,0 +1,74 @@
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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1008 16 h 0 check_sum
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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checksums
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checksum 392 1007 1008
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70
mainboard/artecgroup/dbe63/dts
Normal file
70
mainboard/artecgroup/dbe63/dts
Normal file
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@ -0,0 +1,70 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/{
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mainboard_vendor = "Artec";
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mainboard_name = "DBE62";
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cpus { };
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apic@0 {
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/config/("northbridge/amd/geodelx/apic");
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};
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domain@0 {
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/config/("northbridge/amd/geodelx/domain");
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pci@1,0 {
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/config/("northbridge/amd/geodelx/pci");
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/* Video RAM has to be in 2MB chunks. */
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geode_video_mb = "16";
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};
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pci@1,1 {
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/* This is the graphics device, but since the memory
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* controller needs to know geode_video_mb, the
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* phase2_init is done there. The rest are default ops.
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*/
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};
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pci@1,2 { /* AES */
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};
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pci@f,0 {
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/config/("southbridge/amd/cs5536/dts");
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/* Interrupt enables for LPC bus.
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* Each bit is an IRQ 0-15. */
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lpc_serirq_enable = "0x00001002";
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/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
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lpc_serirq_polarity = "0x0000EFFD";
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/* 0:continuous 1:quiet */
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lpc_serirq_mode = "1";
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/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.
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* See virtual PIC spec. */
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enable_gpio_int_route = "0x0D0C0700";
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/* 0:IDE; 1:FLASH on CS0, 2:FLASH on CS1, 3:FLASH on CS2, 4:FLASH on CS3. */
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enable_ide_nand_flash = "2";
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/* we use com2 since that is on the dongle */
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com2_enable = "1";
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/* Set com2 address to be COM1 */
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com2_address = "0x3f8";
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/* Set com2 IRQ to be what is usually COM1 */
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com2_irq = "4";
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/* USB Port Power Handling setting. */
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pph = "0xf5";
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};
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pci@f,1 {
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/config/("southbridge/amd/cs5536/nand");
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};
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};
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};
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118
mainboard/artecgroup/dbe63/initram.c
Normal file
118
mainboard/artecgroup/dbe63/initram.c
Normal file
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@ -0,0 +1,118 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define _MAINOBJECT
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <msr.h>
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#include <io.h>
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#include <amd_geodelx.h>
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#include <northbridge/amd/geodelx/raminit.h>
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/* #include <device/smbus.h>
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* TODO: figure out how smbus functions should be done. See smbus_ops.c
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*/
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extern int smbus_read_byte(u16 device, u8 address);
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#define MANUALCONF 0 /* Do automatic strapped PLL config */
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#define PLLMSRHI 0x00001490 /* manual settings for the PLL */
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#define PLLMSRLO 0x02000030
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#define DIMM0 ((u8) 0xA0)
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#define DIMM1 ((u8) 0xA2)
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/**
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* Read a byte from the SPD.
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*
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* For this board, that is really just saying 'read a byte from SMBus'.
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* So we use smbus_read_byte(). Nota Bene: leave this here as a function
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* rather than a #define in an obscure location. This function is called
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* only a few dozen times, and it's not performance critical.
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*
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* @param device The device.
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* @param address The address.
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* @return The data from the SMBus packet area or an error of 0xff (i.e. -1).
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*/
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u8 spd_read_byte(u16 device, u8 address)
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{
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u8 spdbyte;
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printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device);
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spdbyte = smbus_read_byte(device, address);
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printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbyte);
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return spdbyte;
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}
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/**
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* Placeholder in case we ever need it. Since this file is a
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* template for other motherboards, we want this here and we want the
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* call in the right place.
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*/
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static void mb_gpio_init(void)
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{
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/* Early mainboard specific GPIO setup */
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}
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/**
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* main for initram for the AMD DB800 development platform.
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* It might seem that you could somehow do these functions in, e.g., the cpu
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* code, but the order of operations and what those operations are is VERY
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* strongly mainboard dependent. It's best to leave it in the mainboard code.
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*/
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int main(void)
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{
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printk(BIOS_DEBUG, "Hi there from initram (stage1) main!\n");
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post_code(POST_START_OF_MAIN);
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system_preinit();
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printk(BIOS_DEBUG, "done preinit\n");
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mb_gpio_init();
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printk(BIOS_DEBUG, "done gpio init\n");
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pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
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printk(BIOS_DEBUG, "done pll reset\n");
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cpu_reg_init(0, DIMM0, DIMM1, DRAM_UNTERMINATED);
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printk(BIOS_DEBUG, "done cpu reg init\n");
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sdram_set_registers();
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printk(BIOS_DEBUG, "done sdram set registers\n");
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sdram_set_spd_registers(DIMM0, DIMM1);
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printk(BIOS_DEBUG, "done sdram set spd registers\n");
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sdram_enable(DIMM0, DIMM1);
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printk(BIOS_DEBUG, "done sdram enable\n");
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/* Check low memory */
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/*ram_check(0x00000000, 640*1024); */
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printk(BIOS_DEBUG, "stage1 returns\n");
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return 0;
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}
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66
mainboard/artecgroup/dbe63/irq_tables.h
Normal file
66
mainboard/artecgroup/dbe63/irq_tables.h
Normal file
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@ -0,0 +1,66 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
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* Copyright (C) 2008 Artec Design LLC.
|
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*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
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#include <pirq_routing.h>
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/* Number of slots and devices in the PIR table */
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#define IRQ_SLOT_COUNT 3
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/* Platform IRQs */
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#define PIRQA 11
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#define PIRQB 10
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#define PIRQC 9
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#define PIRQD 5
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/* Map */
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#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
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#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
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#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
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#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
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/* Link */
|
||||
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
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#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
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#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
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#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
|
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|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
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32 + 16 * IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
|
||||
0x00, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1022, /* Vendor */
|
||||
0x208f, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
|
||||
0xf8, /* Checksum */
|
||||
{
|
||||
/* If you change the number of entries, change IRQ_SLOT_COUNT above! */
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
// Geode GX3 Host Bridge and VGA Graphics
|
||||
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
// Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio.
|
||||
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
|
||||
// Realtek RTL8100/8139 Network Controller
|
||||
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
}
|
||||
};
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||||
71
mainboard/artecgroup/dbe63/stage1.c
Normal file
71
mainboard/artecgroup/dbe63/stage1.c
Normal file
|
|
@ -0,0 +1,71 @@
|
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/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <lib.h>
|
||||
#include <console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <msr.h>
|
||||
#include <io.h>
|
||||
#include <amd_geodelx.h>
|
||||
#include <southbridge/amd/cs5536/cs5536.h>
|
||||
#include <northbridge/amd/geodelx/raminit.h>
|
||||
#include <arch/x86/msr.h>
|
||||
|
||||
static const struct msrinit dbe62_msr[] = {
|
||||
{.msrnum = 0x10000020, {.lo = 0x00fff80, .hi = 0x20000000}},
|
||||
{.msrnum = 0x10000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
|
||||
{.msrnum = 0x40000020, {.lo = 0x00fff80, .hi = 0x20000000}},
|
||||
{.msrnum = 0x40000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
|
||||
};
|
||||
|
||||
static void dbe62_msr_init(void)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < ARRAY_SIZE(dbe62_msr); i++)
|
||||
wrmsr(dbe62_msr[i].msrnum, dbe62_msr[i].msr);
|
||||
}
|
||||
|
||||
void hardware_stage1(void)
|
||||
{
|
||||
post_code(POST_START_OF_MAIN);
|
||||
|
||||
dbe62_msr_init();
|
||||
|
||||
cs5536_stage1();
|
||||
|
||||
/*
|
||||
* NOTE: Must do this AFTER the early_setup! It is counting on some
|
||||
* early MSR setup for the CS5536.
|
||||
*/
|
||||
cs5536_setup_onchipuart(2);
|
||||
|
||||
/* Set up 4MB mode for Artec LPC Dongle (this should be a no-op when not booting from the dongle) */
|
||||
outb(0xf4,0x88);
|
||||
}
|
||||
|
||||
void mainboard_pre_payload(void)
|
||||
{
|
||||
geode_pre_payload();
|
||||
banner(BIOS_DEBUG, "mainboard_pre_payload: done");
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue