They were sized to 32-bit alignment, this grows them to 64 bit-aligned.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie84b2c35b58f186bd8ae993e7ce298332858de05
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23bb036dcb
Original-Change-Id: I494b942c4866a7912fb48a53f9524db20ac53a8c
Original-Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18165
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430618
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The PP1800_S rail is turned off in S3. However, enabling internal
pullups on the pins which are connected to PP1800_S results in
leakage into the P1800_S rail. Fix this by disabling the internal
pullups on PP1800_S rail pins.
BUG=chrome-os-partner:61968
BRANCH=reef
TEST=measured leakage on PP1800_S rail. Gone with this patch.
Change-Id: I5c9a25ca617078a6ad48fe637abf0f397fda1ff5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aa6482e88e
Original-Change-Id: I5ae92b31c1a633f59d425f4105b8db1c9c18c808
Original-Signed-off-by: Aaron Duribn <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18189
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/430614
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
ELAN touchscreen device expects firmware to export GPIOs and ACPI
regulators for managing power to the device. Thus, provide the
required ACPI elements for OS driver to properly manage this device.
BUG=None
BRANCH=None
TEST=Verified that touchscreen works properly on boot-up and after
suspend/resume.
Change-Id: I0b3ec47e93b064f2195ec59bd9b5b8bc1927b3bb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bf68f2286c
Original-Change-Id: I78e0c35f60289afe338d140d90784a433ca534ae
Original-Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18163
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/430612
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As per Audio PCH team recommendation the iDisplay Audio/SDIN2
should be disabled to bypass InitializeDisplayAudio() function
call. Display Audio Codec is HDA-Link Codec, which is not
supported in I2S mode
BUG=chrome-os-partner:61548
BRANCH=none
TEST=Tested to verify that InitializeDisplayAudio() does not
get called.
Change-Id: I5900291ca4b2929db3e09277ffc3dce24d8de6fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 32997fb0bc
Original-Change-Id: Ie0771a8653821e737d10e876313917b4b7c64499
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18091
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430611
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
arm-trusted-firmware comes with another firmware for a coprocessor that
isn't AArch64. When building ATF, make sure to pass our arm(32) compiler
for that purpose.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0fb841a8d434389bc665fd6c133465dfcbba1fde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f34ca46fa6
Original-Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18024
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430717
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, it will print the function name as a prefix to the debug
output. Make it so that a null function name won't get printed, so
that it's possible to print little bits of debug output.
BUG=chromium:683391
BRANCH=none
TEST=build_packages --board=reef chromeos-firmware
Change-Id: I1dff38e4d8ab03118e5f8832a16d82c2d2116ec9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431111
Reviewed-by: Julius Werner <jwerner@chromium.org>
Audio DMIC PLL needs to be ON in S0ix to support
Wake on Voice. This requires GPIO_79 and GPIO_80
to be configured as IGNORE IOSSTATE. So DMIC CLKs
will be ON in S0ix.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id6ddb380477762b37fe0b8fdcac762033048438b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c0eae6112f
Original-Change-Id: If91045a8664ce853366b670b9db38d620818fbab
Original-Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18155
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430713
Currently car_stage_entry is defined only in romstage_after_verstage and
as a result when SEPARATE_VERSTAGE is not selected, there is no
entry point into romstage and romstage will not be started at all.
The solution is move out romstage_after_verstage.S from fsp1.1 driver
to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the
build and boot issue with this change.
Besides that, rename the romstage_after_verstage to romstage_c_entry
in more appropriate naming convention after this fix.
Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0),
romstage can be started successfully.
BUG=none
BRANCH=none
TEST=none
Change-Id: I95a45a090b4a335fa8655c89fbede13d011bb321
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d8e34b2c44
Original-Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd
Original-Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Original-Reviewed-on: https://review.coreboot.org/17976
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/430735
This was already done in upstream when the patch was taken over.
Eliminate the difference.
BUG=none
BRANCH=none
TEST=none
Change-Id: I14545c81d0311130e6756c128b2653a5f92efe16
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427821
It's already available in commonlib/helpers.h
BUG=none
BRANCH=none
TEST=things still build
Change-Id: Ib6e3eff82eb4fe6f3aef2065f5c2f7ada11e9e25
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427820
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
SPI controller need to access flash descriptors/SFDP during s0ix exit,
so all fast SPI IO can't be put into IOSTANDBY state. For reef, that
will be FST_SPI_CLK_FB, GPIO_97, GPIO_99, GPIO_100, GPIO_103 and
GPIO_106.
BUG=chrome-os-partner:61370
BRANCH=reef
TEST=Enter s0ix state in OS, after resume run flashrom to read SPI
content.
Change-Id: Ibeb71637b19c646a3390e98d083ae579144cb31c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8b89252f8a
Original-Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51
Original-Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18137
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430178
Tested-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Combine existing boards google/enguarde and google/ninja using
their common reference board google/rambi as a baseboard.
Variants contain board specific data:
- DPTF ACPI components
- I2C ACPI devices
- RAM config / SPD data
- devicetree config
- GPIOs
- board-specific HW components (e.g., LAN)
Additionally, some minor cleanup/changes were made:
- remove unused ACPI trackpad/touchscreen devices
- correct I2C addresses in SMBIOS entries
- clean up comment formatting
- remove ACPI device for unused light sensor
- switch I2C ACPI devices from edge to level triggered interrupts,
for better compatibility/functionality (and to be consistent
with other recently-upstreamed ChromeOS devices)
The existing enguarde and ninja boards are removed.
Variant setup modeled after google/auron
BUG=none
BRANCH=none
TEST=none
Change-Id: I9129c3d3eda15c1e91ff5bfd0aa5f9f891a2636c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce0a564198
Original-Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18129
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430177
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
The new name and location make more sense:
- The instruction used to call into machine mode isn't called "ecall"
anymore; it's mcall now.
- Having SBI_ in the name is slightly wrong, too: these numbers are not
part of the Supervisor Binary Interface, they are just used to
forward SBI calls (they could be renumbered arbitrarily without
breaking an OS that's run under coreboot).
Also remove mcall_dev_{req,resp} and the corresponding mcall numbers,
which are no longer used.
BUG=none
BRANCH=none
TEST=none
Change-Id: I71a96971f46d515a66d5f77497b40d891c1b5fca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c5ebb1d005
Original-Change-Id: I76a8cb04e4ace51964b1cb4f67d49cfee9850da7
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/18146
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/430174
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
1. Disable WP
2. Pass SD card detect info in ACPI
BUG=chrome-os-partner:60713
BRANCH=None
TEST=Verified that OS is able to detect SD card and read/write to it.
Change-Id: Id16f21dd70798b2e1c6e7af1d163e7089b66b46c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d093e4a387
Original-Change-Id: Ide84d4b86c0fac50a07520dfd76d6d3a921f2ecc
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18138
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430172
poppy schematics have undergone change after review, update
DQS and DQ Byte mappings based on the new schematics.
BUG=chrome-os-partner:61856
BRANCH=None
TEST= Build and boot all the poppy proto SKUs to OS.
Change-Id: I80eab8bc6fb486bab959ab308c93d1d3031247bc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b4a159706e
Original-Change-Id: Ie4532035f37c25540abb26122234f6e3346ede69
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18133
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/430171
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
SBI calls, as it turned out, were never right.
They did not set the stack correctly on traps.
They were not correctly setting the MIP instead of the SIP
(although this was not really well documented).
On Harvey, we were trying to avoid using them,
and due to a bug in SPIKE, our avoidance worked.
Once SPIKE was fixed, our avoidance broke.
This set of changes is tested and working with Harvey
which, for the first time, is making SBI calls.
It's not pretty and we're going to want to rework
trap_util.S in coming days.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1a4fa2ddec9b556ec2da574e080f9a77ef139203
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f3a53b6f6
Original-Change-Id: Ibef530adcc58d33e2c44ff758e0b7d2acbdc5e99
Original-Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/18097
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/430170
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
it may cause edp aux transfer error if set the edp pclk clock too high,
so reduce it to 25MHz.
BUG=chrome-os-partner:60130
BRANCH=None
TEST=Build and Boot
Change-Id: Ibb86c12c1d7c00dc3b4cc7a6bdf3bd6e895cd9f3
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/429410
Commit-Ready: Julius Werner <jwerner@chromium.org>
Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This code allows people to override the usb2 eye pattern
UPD settings for boards.
BUG=chrome-os-partner:61031
BRANCH=None
TEST=Usb2 function ok and make sure fsp upd is overridden
Change-Id: I9e4cc098e5e51f178ab00f7b4d56c4ba099a279c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9d490daf8d
Original-Change-Id: I5fab620a29aba196edf1f24ffe6a1695de1e523e
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18060
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427765
These updated header files contain USB tuning parameters as well as
some general cleanup of unused parameters in the UPD Headers. This
patch along with the upcoming FSP 1.3.0 release will allow for USB
tuning on apollolake platforms.
CQ-DEPEND=CL:*315403
BUG=chrome-os-partner:61031
Change-Id: Icfd57b5358e5598618d7a91af6ba74baddee2fc0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e7056a82e0
Original-Change-Id: Id7cce1ea83057630d508523ada18c5425804535e
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18046
Original-Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427764
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Baytrail SoC has a bug where in some cases the DisplayPort can hang
leading to a non-working display (it just stays black). To avoid this
hang, a patch was introduced in 02/2016
(1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort)
but per default not switched on so that each
mainboard can decide if it wants to use this patch or not.
Recently a new case of this bug was reported by Benoit Sansoni
(benoit.sansoni@kontron.com) and he requested to enable this fix per
default as it costs him a lot of time to find the cause and even the
already available fix in coreboot. To avoid this effort for someone
else in the future we can enable this fix per default as no negative
side effects are known and it is now tested at Siemens and at
Kontron on different mainboards with success.
As the goal is to enable this code permanently the config switch is not
longer needed and is removed.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8865b57dafe5df73e82255367562698b1a0a56b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: deed5fbebd
Original-Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/18109
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428264
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Cosmetic changes to rename car_stage.S to car_stage_fsp20.S,
so that it is associated with FSP driver version that is being used.
Tested on Kabylake Rvp11.
BUG=none
BRANCH=none
TEST=none
Change-Id: I32a6ede3d310f9a48fce42f47d4eeb729abb53da
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 15b7163821
Original-Change-Id: I869df6eb746e3982e5912c272255eab6cb008838
Original-Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18083
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428261
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
To support intel wifi SAR configuration, it is required coreboot
to publish two ACPI objects (WRDS and EWRD) to supply SAR limit
data sets. VPD entry "wifi_sar" is required to supply the raw SAR
limit data.
BUG=chrome-os-partner:60821
TEST=Enable USE_SAR, boot reef to OS, create the VPD entry, reboot,
check the SSDT dump and verify WRDS and EWRD structures.
Change-Id: I3dc4219676f1b4cfb108d15ec25f4c992e0367e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3dea69a487
Original-Change-Id: I6be345735292d0ca46f2f7e7ea61924990d338a8
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://review.coreboot.org/17959
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428260
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Current fw does not create ACPI device for
OS to recognize ELAN touchscreen.
List the touch screen in the devicetree so that
the correct ACPI device are created.
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5aadea9d76
Original-BUG=chrome-os-partner:61803
Original-BRANCH=reef
Original-TEST=emerge-pyro coreboot
Original-Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5
Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18086
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I63d4092acbb26602df9c501b8d87bfb3169ee79d
Reviewed-on: https://chromium-review.googlesource.com/428259
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
mvmap2315_reset() is called from locations where we're checking for NULL
pointers. Because coverity can't tell from the code that the functions
are not returning, it's showing errors of accessing pointers after
we've determined that they're invalid.
Mark it as noreturn, and add a loop in case the reset isn't on the
next instruction. This probably isn't needed, but shouldn't hurt.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icabde50124ed8206a0a114cd10002ef81a770f57
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3051cd9265
Original-Found-by: Coverity Scan #1362809
Original-Change-Id: If93084629d5c2c8dc232558f2559b78b1ca5de7c
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18103
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428257
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Other chips dump tco_status here if it wasn't handled, which makes
sense.
tco_sts can't be zero here, because the call would have already returned
if it were. Also, dump_tco_status wouldn't print anything if tco_sts
were zero.
This will still only print the debug information if DEBUG_SMI is
enabled in Kconfig, so in general, this change won't have much of an
effect on anything.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icfe18802dfe054409e3e0ca111a3a0c272ab2a2d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3e3b858888
Original-Found-by: Coverity Scan #1229598
Original-Change-Id: Id2c69a16817ba18dfa051f514138fbc04a2f7bee
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18101
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428256
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
