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UPSTREAM: driver/intel/fsp1_1: Fix boot failure for non-verstage case

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Currently car_stage_entry is defined only in romstage_after_verstage and
as a result when SEPARATE_VERSTAGE is not selected, there is no
entry point into romstage and romstage will not be started at all.

The solution is move out romstage_after_verstage.S from fsp1.1 driver
to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the
build and boot issue with this change.

Besides that, rename the romstage_after_verstage to romstage_c_entry
in more appropriate naming convention after this fix.

Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0),
romstage can be started successfully.

BUG=none
BRANCH=none
TEST=none

Change-Id: I95a45a090b4a335fa8655c89fbede13d011bb321
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d8e34b2c44
Original-Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd
Original-Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Original-Reviewed-on: https://review.coreboot.org/17976
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/430735
This commit is contained in:
Teo Boon Tiong 2016-12-28 18:56:26 +08:00 • committed by chrome-bot
parent a80f8d7238
commit b21a7cf217
5 changed files with 8 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/drivers/intel/fsp1_1/Makefile.inc
View file

@ -28,7 +28,6 @@ romstage-y += fsp_util.c
romstage-y += hob.c
romstage-y += raminit.c
romstage-y += romstage.c
romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
romstage-y += stack.c
romstage-y += stage_cache.c
romstage-$(CONFIG_MMA) += mma_core.c

2
src/drivers/intel/fsp1_1/car.c
View file

@ -68,7 +68,7 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
}
/* Entry point taken when romstage is called after a separate verstage. */
asmlinkage void *romstage_after_verstage(void)
asmlinkage void *romstage_c_entry(void)
{
/* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
* is still enabled. We can directly access work buffer here. */

2
src/drivers/intel/fsp1_1/include/fsp/car.h
View file

@ -32,7 +32,7 @@ struct cache_as_ram_params {
/* Entry points from the cache-as-ram assembly code. */
asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params);
asmlinkage void after_cache_as_ram(void *chipset_context);
asmlinkage void *romstage_after_verstage(void);
asmlinkage void *romstage_c_entry(void);
/* Per stage calls from the above two functions. The void * return from
* cache_as_ram_stage_main() is the stack pointer to use in RAM after
* exiting cache-as-ram mode. */

1
src/soc/intel/skylake/romstage/Makefile.inc
View file

@ -1,5 +1,6 @@
verstage-y += power_state.c
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage_fsp20.S
romstage-y += pmc.c
romstage-y += power_state.c

8
src/drivers/intel/fsp1_1/romstage_after_verstage.S → src/soc/intel/skylake/romstage/car_stage.S
View file

@ -13,13 +13,15 @@
* GNU General Public License for more details.
*/
#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
/* I/O delay between post codes on failure */
#define LHLT_DELAY 0x50000
.text
.global car_stage_entry
car_stage_entry:
call romstage_after_verstage
#include "after_raminit.S"
call romstage_c_entry
#include "src/drivers/intel/fsp1_1/after_raminit.S"
movb $0x69, %ah
jmp .Lhlt