UPSTREAM: pcengines/apu2: Add SKU in SMBIOS

Installed memory only, PCB revision cannot be detected.

BUG=none
BRANCH=none
TEST=none

Change-Id: I958689da24361763df837e943bb2e03c922f9f84
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 104074994d
Original-Change-Id: Ib6224018db3de4a7ddd9e6f7f30edc438c3f0702
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18153
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430623
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/pcengines/apu2/Makefile.inc

@@ -19,6 +19,7 @@ romstage-y += gpio_ftns.c
 
 ramstage-y += BiosCallOuts.c
 ramstage-y += OemCustomize.c
+ramstage-y += gpio_ftns.c
 
 ## DIMM SPD for on-board memory
 SPD_BIN = $(obj)/spd.bin

src/mainboard/pcengines/apu2/mainboard.c

@@ -28,9 +28,11 @@
 #include <northbridge/amd/pi/00730F01/pci_devs.h>
 #include <southbridge/amd/common/amd_pci_util.h>
 #include <superio/nuvoton/nct5104d/nct5104d.h>
-
+#include <smbios.h>
+#include <string.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
+#include "gpio_ftns.h"
 
 #define SPD_SIZE  128
 #define PM_RTC_CONTROL	    0x56
@@ -188,6 +190,22 @@ static void mainboard_enable(device_t dev)
 	pirq_setup();
 }
 
+/*
+ * We will stuff the memory size into the smbios sku location.
+ */
+const char *smbios_mainboard_sku(void)
+{
+	static char sku[5];
+	if (sku[0] != 0)
+		return sku;
+
+	if (!get_spd_offset())
+		snprintf(sku, sizeof(sku), "2 GB");
+	else
+		snprintf(sku, sizeof(sku), "4 GB");
+	return sku;
+}
+
 struct chip_operations mainboard_ops = {
 	.enable_dev = mainboard_enable,
 };