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UPSTREAM: fsp_baytrail: Enable graphic init per default
Baytrail SoC has a bug where in some cases the DisplayPort can hang leading to a non-working display (it just stays black). To avoid this hang, a patch was introduced in 02/2016 (1c3b1112fa
- fsp_baytrail: Fix a possible hanging DisplayPort) but per default not switched on so that each mainboard can decide if it wants to use this patch or not. Recently a new case of this bug was reported by Benoit Sansoni (benoit.sansoni@kontron.com) and he requested to enable this fix per default as it costs him a lot of time to find the cause and even the already available fix in coreboot. To avoid this effort for someone else in the future we can enable this fix per default as no negative side effects are known and it is now tested at Siemens and at Kontron on different mainboards with success. As the goal is to enable this code permanently the config switch is not longer needed and is removed. BUG=none BRANCH=none TEST=none Change-Id: I8865b57dafe5df73e82255367562698b1a0a56b4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id:deed5fbebd
Original-Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355 Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Original-Reviewed-on: https://review.coreboot.org/18109 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://chromium-review.googlesource.com/428264 Commit-Ready: Aaron Durbin <adurbin@chromium.org>
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3 changed files with 1 additions and 10 deletions
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@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SOC_INTEL_FSP_BAYTRAIL_MD
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select USE_BLOBS
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select CBFS_AUTOGEN_ATTRIBUTES
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select FSP_BAYTRAIL_GFX_INIT
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select USE_SIEMENS_HWILIB
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config MAINBOARD_DIR
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@ -95,14 +95,6 @@ config VGA_BIOS_FILE
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string
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default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS
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config FSP_BAYTRAIL_GFX_INIT
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default n
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bool
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help
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Enabling this option will activate graphics init code. With this init,
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the graphic power gate registers will be initialized before
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VBIOS is executed.
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config CPU_MICROCODE_HEADER_FILES
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string
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default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h"
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@ -57,7 +57,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
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ramstage-y += placeholders.c
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ramstage-y += i2c.c
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ramstage-$(CONFIG_FSP_BAYTRAIL_GFX_INIT) += gfx.c
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ramstage-y += gfx.c
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CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include
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CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
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