The strago build is not well kept after, as it is not used in production;
celes, however, is.
BUG=chromium:734103
TEST=None
Change-Id: Ifdd44d9e5165ff60a013bf610695f65e1ac65b03
Reviewed-on: https://chromium-review.googlesource.com/540139
Commit-Ready: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Richard Barnette <jrbarnette@google.com>
Fixes 2 reports found by undefined behavior sanitizer. Dereferencing
pointers that are not aligned to the size of access is undefiend
behavior.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9f58f4d389569df7a5fa3625b420cd512257582a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d4f994bbc4
Original-Change-Id: Iaa3845308171c307f1ddc7937286aacbd00e3a10
Original-Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Original-Reviewed-on: https://review.coreboot.org/20155
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/539526
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Use define for SSA base address.
Move EM64T area to 0x7c00 and add reserved area of size 0x100,
as there's no indication that the address 0x7d00 exists on any
platform.
No functional change.
BUG=none
BRANCH=none
TEST=none
Change-Id: I40639bb969113332adb27075441bfed974f2c946
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a4677e426a
Original-Change-Id: I38c405c8977f5dd571e0da3a44fcad4738b696b2
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20146
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/539525
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Disable TPM when VBOOT_MOCK_SECDATA is enabled.
BUG=None
BRANCH=None
TEST= Build image using USE="mocktpm" emerge-poppy coreboot depthcharge
vboot_reference chromeos-bootimage . Verify boot is successful with mock
tpm.
Change-Id: I660c1551e067037291164ca2d982c387b4e375b3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1827ec1f4e
Original-Change-Id: Iee527ed17cffb7d25d9089e48a194d99ac8c3cd1
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20158
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539524
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This might provide a minor speedup but more importantly it allows
skipping commits without Reviewed-on line (which we have a couple of
due to mistakes with git push).
To use, add a line starting with "Gerrit-Rebase-Ignore-CLs-Before:"
pointing out a match string (ie "something that comes after Reviewed-on")
prior to which no changes are considered on the originating branch. The
target branch is still fully considered to avoid issues with changes
that were retargetted out of order around the new cut and would then
make a reappearance (or be skipped).
BUG=none
BRANCH=none
TEST=none
Change-Id: I888fb6952f9fafb5541b9a1905678a477e63c76c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 8f8668d87f
Original-Change-Id: I9f2679891e93f6d28a781315aebd2aa60a1e3b23
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://review.coreboot.org/20185
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539523
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Disable NLS for libelf.
BUG=none
BRANCH=none
TEST=none
Change-Id: I62c0118af88a03e6c39d4c45ba7ee2ce23e945bf
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Ignore-CL-Reviewed-on: https://review.coreboot.org/20228
Original-Commit-Id: 9a848dde8b
Original-Change-Id: Ia4d01393771ccdff9e0498d7efd1bbdd11cff8db
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20235
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539234
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The previous implementation was using a for loop. By it's
very definition the last statement in the for loop declaration
is done at the end of the loop. Therefore, if the conditional for
breaking out of the for loop because of a timeout would always
see a value of 0 for the number of APs accepted. Correct this
by changing to a while loop with an explicit timeout condition
at the end of the loop.
BUG=none
BRANCH=none
TEST=none
Change-Id: If8dfd7e5a73480dbd23c29a6e9f07b8369731646
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 046848ce1f
Original-Change-Id: I503953c46c2a65f7e264ed49c94c0a46d6c41c57
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20225
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539233
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch uses common SCS library to setup
sd card.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3ffa66e524e0a37ba4ba87b2a164f73743444624
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a677feca88
Original-Change-Id: I06898e30a9b39f169b35f581a3ee09238f0f40c4
Original-Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20217
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539232
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch uses common SCS library to setup
sd card.
BUG=none
BRANCH=none
TEST=none
Change-Id: I73f3b8d8469cfa7f77c491ff6c7bdf056929378b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 65623b7264
Original-Change-Id: Iafbba04d7a498b9a321e8efee4abf07820d17330
Original-Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19632
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539231
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Create Intel Common SCS code. This code currently only contains
the code for SD card SSDT generation. More code will get added up
in the subsequent phases.
BUG=none
BRANCH=none
TEST=none
Change-Id: I971f86c74a5ee289fe6033d401e40c22fe40526e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 94ee328b97
Original-Change-Id: I82f034ced64e1eaef41a7806133361d73b5009d3
Original-Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19631
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539230
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Use verb table values from AMI firmware, consolidate NID
definitions using azalia macros. Fixes headphone jack detection
and microphone.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7e80ecda87e9a8b406779c3d0f5a278ffc818636
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1e1bbb17a0
Original-Change-Id: Ia31be6efc7afe921ad91b400f66694d951f0a260
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19944
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/539229
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Initialize the audio codec without depending on DSP binary blobs.
The hda_verb.c was copied from the intel/kblrvp rvp7 variant, and the
hda_verb.h file was copied from the purism/librem13.
The IoBufferOwnership FSP option in devicetree has to be 0 for the azalia
driver to work.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2f67ea5ae06166c3f57057b8b0dc4e556c8817b1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: eacac20bd5
Original-Change-Id: Ifa36ac0839daedfa59c497057da0ace04d401f2a
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19943
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539228
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Some NVMe devices (Intel 600p series for example) seem to lock up
in D3 drive power state (L1.2 PCIe power state).
Disabling L1 substates fixes it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I664917f69ab2d60d72dd0896bd110e891f704a48
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d8cbd5633f
Original-Change-Id: I00a327dc91d443beb565fe4e72aaf816e40a007c
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19900
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/539227
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Iade7f4f28f2a8148e4e70f5b5d0948252cfbec82
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 63142153ba
Original-Change-Id: I88e376d61c4aba5030a0be7c8bdfe7b57881a197
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20169
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/539226
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Enable libgfxinit.
Tested on Lenovo T430:
* LVDS
* VGA
* DP (using DP->HDMI adapter)
All three ports are working. The LVDS port is garbled under linux
when VGA or DP is connected, likely due to missing VBT.
BUG=none
BRANCH=none
TEST=none
Change-Id: I998a9b958a273de7331c9ac74a4e15b43be8b0b1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ea6f700632
Original-Change-Id: I665661e93724072d1e8412cfcc0e818f824c8cb0
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20117
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/539225
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Use a GNVS variable to store the trackpad interrupt, in order to
support both SNB and IVB variants from a single build.
BUG=none
BRANCH=none
TEST=none
Change-Id: If873f366e1f760b843950225dfbd3cb1ab275cc7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d3b15c7821
Original-Change-Id: I53df35fff41f52a7d142aea9b1b590c65195bcfd
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20093
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539224
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add a GNVS variable to store trackpad IRQ for google/parrot, so
that both SNB and IVB variants can be built with the same config
BUG=none
BRANCH=none
TEST=none
Change-Id: I66070de2cec7d70f80390557e03692d26a55ef68
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: aff9b30851
Original-Change-Id: I232da4077e3400b8ef2520dc33fd770c731b7ec3
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20092
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539223
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Existing value was copied from librem13 v1 board, use value
obtained from AMI firmware.
TEST: Observe Windows boots correctly, function keys work
under both Windows and Linux.
BUG=none
BRANCH=none
TEST=none
Change-Id: I540b9124a88136993953026c845b8dc58b523682
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 739ded5c18
Original-Change-Id: I0ea6cc4602ce1047cb803acc65cbca1af1f480b0
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19945
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/539222
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Populate a memory_info struct with PEI and SPD data,
in order to inject the CBMEM_INFO table necessary to
populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older
Haswell MRC binary doesn't populate the pei_data struct with
all the info needed, so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
BUG=none
BRANCH=none
TEST=none
Change-Id: I516cf6bb4b341743fea9110e300695d89aac92a2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5aaa8ce21c
Original-Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19958
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/539221
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
- remove unused I2C, serialIO defs
- set PL2 override, VR mailbox cmd based on SKL-U ref board,
as values copied from google/chell are for SKL-Y
BUG=none
BRANCH=none
TEST=none
Change-Id: I2efdc5fb22c2d67fde95f7de37478b9bb1e333e6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2ae2742065
Original-Change-Id: I3a138c28d0322df6cb41ec1a845ae31602cb69a7
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19941
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539219
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Update devicetree USB config based on board spec.
Leave OC pins set to skip since the info is unavailable.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9c6f4ea63dcd09ec9aed4e8ae4ee53d32dcfaf3f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2fa66164d8
Original-Change-Id: I2a4fe17ed7edacbbbaf56969f9d2801b45a20da9
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19940
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539218
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Don't allow the user to set PCIe configspace base address.
Don't allow the user to set the DCACHE size and base.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic14c6b908edb31d371081c49b9388265eda21151
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9c27eda052
Original-Change-Id: I7a42cc5f6098214364624bcfa3cbd93b4903ee84
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20181
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539217
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I584088ba0b02411b8c59c6a5d84d1aa27bfd883f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 432ac615d0
Original-Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20180
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539216
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I6960f16a67860c0521be4eb621d028cfda7775ee
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 24c3fef31b
Original-Change-Id: I8b2794f56f39492589a08e5676cb33eec89a976e
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20179
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539215
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I0890bbb69183f2ec11c0c2fc3114ac29ee7321d3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 48d6b76d53
Original-Change-Id: I254549057552be93611afa8ca52d22be220fe3dc
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20178
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539214
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Does not need to changeable in menuconfig.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0bef7f608ed615d4c32dfbe475d424ad3680341c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3038b48de3
Original-Change-Id: Id488f7333952d10d10a62ac75298ec8008e6f9b4
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20177
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539213
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
While building poppy board, build failed with following error message:
Writing new image to build/coreboot.pre.new
mv build/coreboot.pre.new build/coreboot.pre
util/me_cleaner/me_cleaner.py -c build/coreboot.pre > /dev/null
This image does not contains a ME/TXE firmware NR = 0)
make: *** [src/southbridge/intel/common/firmware/Makefile.inc:55:
add_intel_firmware] Error 1
Hence keeping CHECK_ME unset by default.
TEST=Succesfully built coreboot for Poppy & booted to OS.
Change-Id: Ie6de9fb169ae2225430651fe35109178194f20d3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 95d6dd21c9
Original-Change-Id: Ib3186498c8da307b686c06c3828e24acbc7f2d17
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19257
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539212
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This reverts commit f4835a85c0. It
completely ignores port coalescing and breaks enumeration in many
cases. The code reused to disable and hide the root ports was never
meant to be called that way.
The same effect of power saving can likely be achieved by clock
gating unused ports after enumeration without further, error-prone
function hiding.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibb8c6c2143324a3d366d838234ae0b2fe317fdaa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fc20926130
Original-Change-Id: I90d8b9236004f0c42d5a2b6bbd39f6dea07bd3d1
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/20216
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/539211
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
A major regression was introduced with commit 6520e01a
(soc/intel/apollolake: Perform CPU MP Init before FSP-S Init)
where the APs execution context is taken away by FSP-S. It
appears that FSP-S is not honoring the SkipMpInit UPD because
it's been shown with some debug code that FSP-S is compeltely
hijacking the APs:
Chrome EC: Set WAKE mask to 0x00000000
Chrome EC: Set WAKE mask to 0x00000000
CBFS: 'VBOOT' located CBFS at [440000:524140)
CBFS: Locating 'vbt.bin'
CBFS: Found @ offset 2e700 size 1a00
Running FSPS in 4 secs.. 315875 4315875
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
Running FSPS.. 4315875 4315875
ITSS IRQ Polarities Before:
ITSS IRQ Polarities Before:
IPC0: 0xffffeef8
IPC1: 0xffffffff
IPC2: 0xffffffff
IPC3: 0x00ffffff
ITSS IRQ Polarities After:
IPC0: 0xffffeef8
IPC1: 0x4a07ffff
IPC2: 0x08000000
IPC3: 0x00a11000
This is essentially a revert of 6520e01a to fix the previous
behavior.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id678f145584418e76d0ffbb9884e58e6e55db9b6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ac3e48257e
Original-Change-Id: I2e136ea1757870fe69df532ba615b9bfc6dfc651
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20215
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539210
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
TEST=Verified that board still boots to OS without any error.
Change-Id: I44c002e71e85017599a3f474941ced51c79e44d3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 296c79c9be
Original-Change-Id: I02d2a6cbcab92766a35993bfd20aaeed4ca22c90
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20143
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/539209
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Now that we dynamically disable TPM interface based on config options,
add support for generation of SPI TPM ACPI node if SPI TPM is used.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie64165f4b10fdae8ab64267f713a1feaaf1594c6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dec6d4e8c7
Original-Change-Id: I87d28a42b48ba916c70e45a061c5efd91a8a59bf
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20142
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539208
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Based on the config options selected, decide at runtime which TPM
interface should be disabled so that ACPI tables are not generated for
that interface.
TEST=Verified that unused interface does not show up in ACPI tables.
Change-Id: I62356b4f834c95f4d5a6982c9e2d1d2131d68092
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b2f423578e
Original-Change-Id: Iee8f49e484ed024c549f60c88d874c08873b75cb
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20141
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539207
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
If I2C device is disabled:
1. BAR for the device will be 0
2. There is no need to generate ACPI tables for the device
TEST=Verified that if an i2c device is disabled statically in
devicetree or dynamically in mainboard, then coreboot does not die
looking for missing resources.
Change-Id: I3617894691853f18b1ebb6f1fe26202d8d3ff502
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d629e433dd
Original-Change-Id: Id9a790e338a0e6f32c199f5f437203e1525df208
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20140
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539205
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Initial support for undefined behavior sanitizer in ramstage. Enabling
this will add -fsanitize=undefined to the compiler command line and
link with ubsan.c in ramstage. Code with UB triggers a report with
error, file, and line number, then aborts.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifa0436eda099cceb1d238a1006d47c7d86793e10
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ab37e9a171
Original-Change-Id: Ib139a418db97b533f99fc59bcb1a71fb6dcd01d8
Original-Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Original-Reviewed-on: https://review.coreboot.org/20156
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539204
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fixes report found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= width of type is undefined. Add
ul suffix since it's safe for unsigned types.
BUG=none
BRANCH=none
TEST=none
Change-Id: I76262ee24dc89fac3d2b027ded72f1f32afaa580
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fce582fa1c
Original-Change-Id: I4b2365428e421085285006bc1ea8aea75890ff65
Original-Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Original-Reviewed-on: https://review.coreboot.org/20144
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539203
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fixes report found by undefined behavior sanitizer. Dereferencing a
pointer that is not aligned to the size of access is undefined behavior.
Switch to memcpy() for unaligned write to EBDA_LOWMEM. Change other
write16()s in setup_ebda() to memcpy() for consistency.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic28f2b8d8b84a71b65ceb1a47015eef99a95319a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f0b0712023
Original-Change-Id: I79814bd47a14ec59d84068b11d094dc2531995d9
Original-Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Original-Reviewed-on: https://review.coreboot.org/20132
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539202
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
USB port status register can be used to decide if a particular port
was responsible for generating PME# resulting in device wake:
1. CSC bit is set and port is capable of waking on connect/disconnect
2. PLC bit is set and port is in resume state
BUG=b:37088992
TEST=Verified with wake on USB2.0 port 3, mosys shows:
19 | 2017-06-08 15:43:30 | Wake Source | PME - XHCI (USB 2.0 port) | 3
Change-Id: I5e566b106bf896ca278a4ccf552d4d4be69736f0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ef08545bff
Original-Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20122
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/539201
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Also changes the arguments of some functions to const.
This reduces romstage size by a whopping 1009 bytes.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7f0aba95153bf8aa822900880001d46049e966c1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6bf13012c1
Original-Change-Id: I054504412524b7be19d98081097843b61bc0c459
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20147
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539200
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.
This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).
Also remove cpu_reset() completely since it's not used anywhere and
doesn't seem very useful compared to the others.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaa2ba1292cb6dc1a4a8098ee256044691f42daba
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 01f9aa5e54
Original-Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19789
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539199
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
If an MTRR solution exceeds the number of available MTRRs
don't attempt to commit the result. It will just GP fault
with the MSR write to an invalid MSR address.
BUG=none
BRANCH=none
TEST=none
Change-Id: I93cca7a563bc70aaa5d13163a37c89cd53605aac
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d9762f70ac
Original-Change-Id: I5c4912d5244526544c299c3953bca1bf884b34d5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20163
Original-Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539198
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
AMD_FAM10H code enables early cbmem by default.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie52b4f096e2bd77ca6cd8fe12f3d3f9d0bf472be
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e1058c7c99
Original-Change-Id: Ifad007f6604bb612d544cf1387938a8fef1cceb4
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20148
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539197
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Since this mainboard provides 3 COM ports on LPC, enable decoding of the
corresponding address range for COM 3.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iae09fc6a1ef0457322c9d5c84fefcd06832bf248
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a00d84536b
Original-Change-Id: I15c0748fce67eef46401c314f441aa45f5e3c5fa
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/20162
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/539196
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The 'set' field was not used anywhere. Replace the struct with a simple
integer representing the mask.
initializer updates performed with:
sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04]? ?\}/0\1/g' \
src/ec/*/*/ec.c
sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04] ?\}/0\1/g' \
src/ec/*/*/ec_lpc.c \
src/superio/*/*/superio.c \
src/superio/smsc/fdc37n972/fdc37n972.c \
src/superio/smsc/sio10n268/sio10n268.c \
src/superio/via/vt1211/vt1211.c
src/ec/kontron/it8516e/ec.c was manually updated. The previous value for
IT8516E_LDN_SWUC appears to have been a typo, as it was out of range and
had a zero bit in the middle of the mask.
BUG=none
BRANCH=none
TEST=none
Change-Id: I40ce1f7f62ac7e9b82b974d314a8bc2335cf8cb7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7daac91236
Original-Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9
Original-Signed-off-by: Samuel Holland <samuel@sholland.org>
Original-Reviewed-on: https://review.coreboot.org/20078
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Myles Watson <mylesgw@gmail.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539195
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
- use Siemens NC FPGA driver for backlight brightness and PWM control
- set Dsave time for board reset after falling edge of signal xdsave
BUG=none
BRANCH=none
TEST=none
Change-Id: I6a51fce1d40d68dc2953a5f49213076f734121d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c21ba2cd3e
Original-Change-Id: I5077d4af162e54a3993e5e0d784a8356f51bd0c9
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/20161
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/539194
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The siemens/mc_apl1 mainboard needs more functionality provided by
Siemens NC FPGA. The additional functionality contains backlight
brightness/PWM control and Dsave time for board reset.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib9b98e0c5c9a350f84a0f520df3ec37a94760d8a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c4ff1de8bf
Original-Change-Id: I6b65b01f0d67afe598b7c005868f71b00dec56fd
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/20160
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/539193
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The Siemens mc_apl1 mainboard needs new values from hwilib.
- add Dsave time for board reset
- add backlight brightness for panel setting
- add backlight PWM period
BUG=none
BRANCH=none
TEST=none
Change-Id: Idc3c86ccbd1d16f9b3ddd46a556a19dbe83f6dcf
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 59dd466414
Original-Change-Id: I3a48654ef57c7f8accaabe60e8aec144e4fe5466
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/20159
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/539192
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The board dutifully registers an int15h handler and provides the
defaults to add a VGABIOS.
That should be good enough to initialize graphics through the VGABIOS
file.
Fixes build on Chrome OS configurations (at least until the Ada toolchain
situation is resolved over there).
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib535d95885606decf029206e615817a774e25029
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1d3661be0a
Original-Change-Id: I1d956b5a163b7cdf2bd467197fba95f16e5e8fa3
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://review.coreboot.org/20218
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/538580
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Use common init_igd_opregion method and remove duplicated code in
acpi.c.
BUG=none
BRANCH=none
TEST=none
Change-Id: I27da90bcdeabd10454b16e366a47d3fb46bd57ad
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9aca643ccb
Original-Change-Id: I811e8bd2be68813321dc4581af02e1c21b0da076
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19910
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/538579
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
