Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: soc/intel/skylake: Add missing PCH_DEV_* definitions

Browse source 
BUG=none
BRANCH=none
TEST=none

Change-Id: I4cea3f1c9f9084312f0f0c91028425b68d2c31c2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 268eea0e41
Original-Change-Id: Ib7aa495ccfd405d6ffc968388c28dc540da2f525
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20203
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/539206
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Furquan Shaikh 2017-06-13 14:37:08 -07:00 • committed by chrome-bot
parent 46f2add6c0
commit b99994198e
1 changed files with 6 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/soc/intel/skylake/include/soc/pci_devs.h
View file

@ -52,6 +52,7 @@
#define PCH_DEV_SLOT_ISH 0x13
#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0)
#define PCH_DEV_ISH _PCH_DEV(ISH, 0)
#define PCH_DEV_SLOT_XHCI 0x14
#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
@ -61,6 +62,7 @@
#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
#define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1)
#define PCH_DEV_THERMAL _PCH_DEV(XHCI, 2)
#define PCH_DEV_CIO _PCH_DEV(XHCI, 3)
#define PCH_DEV_SLOT_SIO1 0x15
#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0)
@ -134,7 +136,10 @@
#define PCH_DEVFN_SDCARD _PCH_DEVFN(STORAGE, 6)
#define PCH_DEV_UART0 _PCH_DEV(STORAGE, 0)
#define PCH_DEV_UART1 _PCH_DEV(STORAGE, 1)
#define PCH_DEV_GSPI0 _PCH_DEV(STORAGE, 2)
#define PCH_DEV_GSPI1 _PCH_DEV(STORAGE, 3)
#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 4)
#define PCH_DEV_SDIO _PCH_DEV(STORAGE, 5)
#define PCH_DEV_SDCARD _PCH_DEV(STORAGE, 6)
#define PCH_DEV_SLOT_LPC 0x1f
@ -153,6 +158,7 @@
#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)
#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
#define PCH_DEV_GBE _PCH_DEV(LPC, 6)
#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7)
static inline int spi_devfn_to_bus(unsigned int devfn)
{