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UPSTREAM: soc/intel/apollolake: Removing some menuconfig options

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Does not need to changeable in menuconfig.

BUG=none
BRANCH=none
TEST=none

Change-Id: I0bef7f608ed615d4c32dfbe475d424ad3680341c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3038b48de3
Original-Change-Id: Id488f7333952d10d10a62ac75298ec8008e6f9b4
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20177
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539213
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Arthur Heymans 2017-06-13 14:05:09 +02:00 • committed by chrome-bot
parent bd73d0ddf0
commit 97bc829c53
1 changed files with 3 additions and 3 deletions
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6
src/soc/intel/apollolake/Kconfig
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@ -113,11 +113,11 @@ config PCR_BASE_ADDRESS
This option allows you to select MMIO Base Address of sideband bus.
config DCACHE_RAM_BASE
hex "Base address of cache-as-RAM"
hex
default 0xfef00000
config DCACHE_RAM_SIZE
hex "Length in bytes of cache-as-RAM"
hex
default 0xc0000
help
The size of the cache-as-ram region required during bootblock
@ -140,7 +140,7 @@ config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
config CONSOLE_UART_BASE_ADDRESS
depends on CONSOLE_SERIAL
hex "MMIO base address for UART"
hex
default 0xde000000
config SOC_UART_DEBUG