UPSTREAM: soc/intel/common/block: Add Intel common SCS code support

Create Intel Common SCS code. This code currently only contains
the code for SD card SSDT generation. More code will get added up
in the subsequent phases.

BUG=none
BRANCH=none
TEST=none

Change-Id: I971f86c74a5ee289fe6033d401e40c22fe40526e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 94ee328b97
Original-Change-Id: I82f034ced64e1eaef41a7806133361d73b5009d3
Original-Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19631
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539230
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>

src/soc/intel/common/block/include/intelblocks/sd.h

@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_SD_H
+#define SOC_INTEL_COMMON_BLOCK_SD_H
+
+#include <arch/acpi_device.h>
+
+/*
+ * Fill the GPIO Interrupt or I/O information that will be used for the
+ * GPIO Connection Descriptor.
+ */
+int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_SD_H */

src/soc/intel/common/block/scs/Kconfig

@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_SCS
+	bool
+	help
+	  Intel Processor common storage and communication subsystem support

src/soc/intel/common/block/scs/Makefile.inc

@@ -0,0 +1 @@
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += sd.c

src/soc/intel/common/block/scs/sd.c

@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpigen.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <intelblocks/sd.h>
+
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+static void sd_fill_ssdt(struct device *dev)
+{
+	const char *path;
+	struct acpi_gpio default_gpio = { 0 };
+	struct acpi_dp *dp;
+
+	if (!dev->enabled)
+		return;
+
+	if (sd_fill_soc_gpio_info(&default_gpio, dev) != 0)
+		return;
+
+	/* Use device path as the Scope for the SSDT */
+	path = acpi_device_path(dev);
+	if (!path)
+		return;
+	acpigen_write_scope(path);
+	acpigen_write_name("_CRS");
+
+	/* Write GpioInt() as default (if set) or custom from devicetree */
+	acpigen_write_resourcetemplate_header();
+	acpi_device_write_gpio(&default_gpio);
+	acpigen_write_resourcetemplate_footer();
+
+	/* Bind the cd-gpio name to the GpioInt() resource */
+	dp = acpi_dp_new_table("_DSD");
+	if (!dp)
+		return;
+	acpi_dp_add_gpio(dp, "cd-gpio", path, 0, 0, 1);
+	acpi_dp_write(dp);
+
+	acpigen_pop_len();
+}
+#endif
+
+static struct device_operations dev_ops = {
+	.read_resources		  = &pci_dev_read_resources,
+	.set_resources		  = &pci_dev_set_resources,
+	.enable_resources	  = &pci_dev_enable_resources,
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+	.acpi_fill_ssdt_generator	= &sd_fill_ssdt,
+#endif
+};
+
+static const unsigned short pci_device_ids[] = {
+	PCI_DEVICE_ID_INTEL_APL_SD,
+	PCI_DEVICE_ID_INTEL_GLK_SD,
+	PCI_DEVICE_ID_INTEL_SKL_SD,
+	0
+};
+
+static const struct pci_driver pch_sd __pci_driver = {
+	.ops	= &dev_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.devices	= pci_device_ids
+};