With change dd82edc388 (lib/spd_bin: make SMBus SPD addresses an
input), SMBus SPD addresses are accepted from the mainboard and not
calculated within the spd_bin library routines. Use the addr_map
values to print correct address in dump_spd_info.
BUG=none
BRANCH=none
TEST=none
Change-Id: I90ce930c23cd49ff93e4d5c8067810ee77598b86
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a26f9da6ba
Original-Change-Id: Iff37e382aeac9704f74bafc2ecb27f14c478723f
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20118
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Shelley Chen <shchen@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531712
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch makes SOC files to use common/block/cpu/cpulib.c
file's helper functions.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie18eb7e9cff4053792706cd7c467e1a2b1347345
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 66fe0c43be
Original-Change-Id: I529c67cf20253cf819d1c13849300788104b083c
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19827
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531711
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The supported "G41C-GS" with a nuvoton nct6776 superio is actually
G41C-GS R2.0, which is different with the more easily-found revision
G41C-GS (R1.0) with Winbond W83627DHG superio, and should be ported
separately.
Photos for the two revision:
R1.0: https://web.archive.org/web/20160915160553/http://www.asrock.com/mb/photo/G41C-GS(L1).jpg
R2.0: https://web.archive.org/web/20160717203810/http://www.asrock.com/mb/photo/G41C-GS%20R2.0(L2).jpg
BUG=none
BRANCH=none
TEST=none
Change-Id: If8236eacdc35b3b22d813265e678f0321878bfee
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1517bab693
Original-Change-Id: If60a694bcf0652ab32c0ac75ceec7e27e11fe9eb
Original-Signed-off-by: Bill XIE <persmule@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19980
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/531710
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Rename these two Macros to help use Common Code -
ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS
ACPI_PMIO_SIZE --> ACPI_BASE_SIZE
BUG=none
BRANCH=none
TEST=none
Change-Id: I2d61fac058531f45d9133578c818440ed4c5ea93
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9e55ff6a87
Original-Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20038
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531709
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch enables ACPI timer emulation on all the logical cpus.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Verify MSR 0x121 gets programmed on all logical cpus during coreboot MP Init.
Change-Id: Ic11a9038769abdca530a7f6fc36695c4638d9487
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f004f66ca7
Original-Change-Id: I2246cdfe1f60fd359b0a0eda89b4a45b5554dc4a
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18288
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531708
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch makes SOC files to use common/block/cpu/cpulib.c
file's helper functions.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia0328783f3365d1ec06dd87b1e744e5c4d4871ec
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0a203d13f6
Original-Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19566
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531707
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Create Intel Common CPU library code which provides various
CPU related APIs.
This patch adds cpulib.c file which contains various helper
functions to address different CPU functionalities like -
cpu_set_max_ratio(),
cpu_get_flex_ratio(),
cpu_set_flex_ratio(),
cpu_get_tdp_nominal_ratio(),
cpu_config_tdp_levels(),
cpu_set_p_state_to_turbo_ratio(),
cpu_set_p_state_to_nominal_tdp_ratio(),
cpu_set_p_state_to_max_non_turbo_ratio(),
cpu_get_burst_mode_state(),
cpu_enable_burst_mode(),
cpu_disable_burst_mode(),
cpu_enable_eist(),
cpu_disable_eist(),
cpu_enable_untrusted_mode()
BUG=none
BRANCH=none
TEST=none
Change-Id: I14bbfb9d3198ca46470d04edcb74d7d43e709034
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 19b546f48c
Original-Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19540
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/531706
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
As per BWG, CPU MP Init (loading ucode) should be done prior
to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry
(before FSP-S call).
BUG=none
BRANCH=none
TEST=Build and boot Reef
Change-Id: Ie3165594c63cf657d4079867b5b2c7fab2cd8649
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6520e01a46
Original-Change-Id: I49f336c10d6afb71f3a3b0cb8423c7fa94b6d595
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20037
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531705
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Since get_microcode_info() is aleady searching for the microcode in cbfs,
we can just add a intel_microcode_load_unlocked() call here to update
the microcode. No need to duplicate finding microcode step during
pre_mp_init() function.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id9bb31b2b02dd92dadb76cbd37bf1f5e01b64117
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 97daf98806
Original-Change-Id: I525cab0ecc7826554f0a1209862e6357d1c7a9a6
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20088
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/531704
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
FIT is already loading microcode before CPU Reset. So, we need
not update the microcode again in RO FW in bootblock.
But we need to update in RW FW if there is any new ucode version.
So, added the update microcode function in get_microcode_info callback
before MP Init to make sure BSP is using the microcode from cbfs.
BUG=none
BRANCH=none
TEST=Build and Boot poppy
Change-Id: I7665b2f1fc10f625f8535aef1f11a77154dfe2a4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 682355ab16
Original-Change-Id: I5606563726c00974f00285acfa435cadc90a085e
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20051
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/531703
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
If the boot media is memory mapped temporarily mark it as write
protect MTRR type so that memory-mapped accesses are faster.
Depthcharge payload loading was sped up by 75ms using this.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icca415dceef9b20728294a890e908905e4208636
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 93d5f40be5
Original-Change-Id: Ice217561bb01a43ba520ce51e03d81979f317343
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20089
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531702
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The fast_spi_cache_bios_region() does the necessary lookup
of BIOS region size, etc. Don't inline the calculation and
just defer to the common piece of code for memory-mapped
spi flash boot.
BUG=none
BRANCH=none
TEST=none
Change-Id: I47744f71cad87b908f8f672930c6c4d1716e04c7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: efc92a86c2
Original-Change-Id: I6c390aa5a57244308016cd59679d8c3ab02031b8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20116
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531701
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
After the MTRR solution has been calculated provide a way
for code to call the same function, fast_spi_cache_bios_region(),
in all stages. This is accomplished by using the ramstage
temporary MTRR support.
BUG=none
BRANCH=none
TEST=none
Change-Id: I05bb30b98455539fe5aed7e25b44bee185918744
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0b34fc6f54
Original-Change-Id: I84ec90be3a1b0d6ce84d9d8e12adc18148f8fcfb
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20115
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531700
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Like the previous commit allow the declarations of functions to
be exposed to all stages unless ROMCC is employed.
BUG=none
BRANCH=none
TEST=none
Change-Id: I174399f6957768e57d3cc87a157b260632ef45eb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ea0497c786
Original-Change-Id: Ie4dfc32f38890938b90ef8e4bc35652d1c44deb5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20114
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531699
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fix line over 80 characters warnings and space after function name
warning.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9a9685c2789b181a23de4d8f253cec5df318d889
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: acd02b5b3f
Original-Change-Id: Id5a5abaa06f8e285ff58436789318cb9cd3b7ac3
Original-Signed-off-by: Evelyn Huang <evhuang@google.com>
Original-Reviewed-on: https://review.coreboot.org/19988
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531698
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch perform resource mapping for PCI,
fixed MMIO, DRAM and IMR's based on inputs given by SoC.
TEST=Ensure PCI root bridge 0:0:0 memory resource allocation
remains same between previous implementation and current
implementation.
Change-Id: I3638c07cbbc15025f7bc2b1f573ebc5f7f816fb6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 208587e0f6
Original-Change-Id: I15a3b2fc46ec9063b54379d41996b9a1d612cfd2
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19795
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531697
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch perform resource mapping for PCI,
fixed MMIO, DRAM and IMR's based on inputs given by SoC.
TEST=Ensure PCI root bridge 0:0:0 memory resource allocation
remains same between previous implementation and current
implementation.
Change-Id: I180d06e3b465e369eb24c1711e48aaf2f59a858a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 46a7178267
Original-Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19796
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531696
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add Intel common systemagent support for romstage and ramstage.
Include soc specific macros need to compile systemagent common code.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9af8a5134f382fbfe94945e81adbf15ec97b1a6a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7609c654b1
Original-Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c
Original-Signed-off-by: V Sowmya <v.sowmya@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19668
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531695
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
cherry-pick from Chromium, commit 8fbe1e7
On Braswell and Baytrail devices, by userland 'perf top',
observed demanding clocks on __vdso_clock_gettime() since
chromeos_3.18 kernel; besides, evaluated massive calling of
clock_gettime() cost, up to 700 ns in average.
It turns out that Linux kernel of map_vdso() first call of
remap_pfn_range() does not fall into reserve_pfn_range()
due to size parameter, instead it relies on lookup_memtype()
and potentially be failed to be identified as eligible RAM
resource because the function of pat_pagerange_is_ram() actually
walks through root's sibling.
Meanwhile, on current BSW (and BYT) firmware implementation
makes System RAM resources located on child leaf, combining all
of these factors makes the kernel treat the vvar page of vdso
as a uncached-minus one leading slow access in result.
This patch recollects TOLM accessing; as Aaron recalled some
core_msr_script turns off access to TOLM register, he suggests
to store tolm to avoid getting back a zero while setting acpi
nvs space.
Original-Change-Id: Iad4ffa542b22073cb087100a95169e2d2a52efcd
Original-Signed-off-by: Harry Pan <harry.pan@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/368585
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I60646b49268db162deac8614cc80e5712a358ad0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 43dcbfd855
Original-Change-Id: Idc9765ec5c0920dc98baeb9267a89bec5cadd5a0
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20060
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531694
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Update devicetree PCI config based on board spec:
- enable PCIe Root Ports 5 and 9 (wifi and nvme respectively)
- enable PCIe CLKREQ on RP9, disable on RP5
- enable USB OTG
- enable P2SB
Note: PCIe RP5 is on 0.1c.0 despite this being labeled as RP1
BUG=none
BRANCH=none
TEST=none
Change-Id: I8883f75cc65b56dc22e38ec5513149c0d9205137
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: debb785d59
Original-Change-Id: Ia71ed25bd41668df1ee3e4b4e28f54482722452c
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19939
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531693
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Needed for UEFI booting via Tianocore;
with PM timer disabled, payload hangs.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0ac172b90f496e44b117e3ec9a3809d7708b85b6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0ff3b73990
Original-Change-Id: I6c65cb9d3e6a10baea4cc1e2d9e94c36fe419561
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19938
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531692
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I34e5babc9b6f059d73d02348ad0fbcff07563527
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9d8cd507a6
Original-Change-Id: Ib63e5e8a1bcbc25c288dec7d1ef6c06239ada34b
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19937
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531691
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The FSP Temp RAM init will fail if the mircocode values are set
to 0. A valid microcode update needs to be included and its size
and offset need to be set in the config.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iac912e7350662a9e56aae6eb80b70fca5c032fd3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6b8570d864
Original-Change-Id: I26d05bd7b37c8d91bf34f399c7c4189f9d3dd34a
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19936
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531690
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Adding code to setup the spd information from sodimm.
Adapted from intel/kblrvp.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iffd47fc71def3533fb7545abe753fd09df77e184
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0e977fca9c
Original-Change-Id: I0403f999dac1bdef0e9e1abe7c9c62407e223bb1
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19935
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531689
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The GPIO configuration matches the one from the original BIOS.
Some configs don't make much sense, but I kept it as is so it
would match (such as a NC pin with TX set to 1, or RXINV enabled).
Remove unnecessary early GPIO config.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id7d3d5537260431af116b017ad5860d95adf781c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 34a30a648f
Original-Change-Id: Iaec8630cef9a523fb2e2503143aa4aa72fbedc1f
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19934
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531688
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Like other devices using ENE embedded controllers, the librem13v2
requires this config option for the PS2 keyboard and mouse
(trackpad) to function properly.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6a4309052ac05fafe88e7ec61e52dcdb5a320559
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2766ebf585
Original-Change-Id: Ifba13b93a1fe2e76b2790d1c273fd9e2b5368ab0
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19933
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531687
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add the initial directory for the port of the Librem 13 v2.
The base implementation was copied from the google/chell directory
and the chell references were replaced. spd directory was removed
since the RAM is not soldered on the MB. The Kconfig, board_info.txt
and devicetree.cb files were modified to match the Librem 13 v2
hardware information. The romstage.c, mainboard.c, Makefile.in and
dsdt.asl were modified to remove chromeos specific code. The boardid.c,
chromeos.c, chromeos.fmd, cmos.layout, ec.c, ec.h and smihandler.c
files were removed from the tree, and the acpi directory was replaced
with the acpi directory from the purism/librem13 board.
These changes allow us to remove the references to chromeos specific
code and allow coreboot to compile when the librem13v2 board is selected.
BUG=none
BRANCH=none
TEST=none
Change-Id: I44e7be967bf4e72e086aa26d332ac6dd16ae0608
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 047475cbd7
Original-Change-Id: I24263fde18fcea70163dbdc59df6ea1d98c97af8
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19932
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531686
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The FADT revision was set to 5, but we do not implement the
ACPI v5.0 specification, which prevents Windows from booting.
Setting it to v3 (matching most other boards) fixes the issue
and Windows now boots normally.
Bug found by Matt DeVillier, fix tested by Youness Alaoui on
Librem 13 v1 hardware.
Please also see commits 00d250e228 (intel/skylake: Switch FADT
to ACPI version 3.0) [1] and 27e6042bb7 (intel/apollolake:
Switch FADT to ACPI version 3.0) [2].
[1] https://review.coreboot.org/19453
[2] https://review.coreboot.org/19146
BUG=none
BRANCH=none
TEST=none
Change-Id: I24a5d1d75ef0fca5b273d8d32d20812089850812
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ab5b4c19c3
Original-Change-Id: Ide97cbf64f7b05018433436431ab4723b217fe22
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19985
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531685
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The Role-Based Error Reporting is not a configurable field,
it's a read only field in the Device Capability register.
This code was old and comes from commit f6eb88ad but evidently
is not useful in any way. The PCIe Specification [1] states
that it's read-only and must always be set to 1.
I have also done tests on purism/librem13 hardware, trying to
change that value, without any success.
[1]: PCI Express Base Specification Revision 3.0
Page 612
BUG=none
BRANCH=none
TEST=none
Change-Id: Id4dff17957fbd6e1f54ab0917d4f9c7b557149d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2f48b7b1e9
Original-Change-Id: I729617a5c6f4f52dfc4c422df78379b309066399
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19901
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531684
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The ASPM options (L1 substates, CLKREQ support, Common Clock and ASPM)
are hardcoded for broadwell chips, but some boards may not support
these ASPM options even if the SoC does support it (non-wired CLKREQ
pin for example).
This is required to disable L1 substates on the Purism/Librem 13 which
seems to have issues with NVMe drives falling into L1.2 state and not
being able to exit that state.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifde46a1db3702a6e1ad49cf3cb03a61d6ffe82d4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b191c9f0ab
Original-Change-Id: I2c7173af1d482cccdc784e3fa44ecbb5d38ddc34
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19899
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531203
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The PCIe specification[1] describes a race condition that
can occur when using the Retrain Link bit in the Link
Control Register.
The race condition is avoided by checking the retrain link
bit in the link status register and waiting until it is
set to 0, before initiating a new link retraining.
[1] PCI Express Base Specification Revision 3.0
Page 633
BUG=none
BRANCH=none
TEST=none
Change-Id: I9ebdb696f63706590bf864f4b3e11304a1f7a1b4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bb5fb64e11
Original-Change-Id: I9d5840fb9a6e63838b5a4084d3bbe483f1d870ed
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19556
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531202
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
A simple rename of the directory and the config values
and string in Kconfig/Kconfig.name/board_info.txt
It will be less confusing for users since the first models
are referred to as 'v1' everywhere now.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7a5bc84a564a6e75f0be9b34957ec09031fd368c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3c0d7d21ef
Original-Change-Id: I23fa977717230c2001868741bb684e9633a2c0bb
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19931
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/531201
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Adapted from Chromium commit 8fbe1e7 for soc/braswell
(also review.coreboot.org/#/c/20060/); same issue affects
baytrail as well.
This patch recollects TOLM accessing; as Aaron recalled some
core_msr_script turns off access to TOLM register, he suggests
to store tolm to avoid getting back a zero while setting acpi
nvs space.
BUG=none
BRANCH=none
TEST=none
Change-Id: I87cc97e3d8270801b6924b310919ad7293f17626
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f05d2e17b0
Original-Change-Id: Ib26d4fe229b3f7d8ee664f5d89774d1f4a997f51
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20081
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531200
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Each I2C controller should have a unique pair of DMA request lines,
and DMA channels should be assigned incrementally, rolling over as
necessary.
Source: Intel Baytrail/ValleyView UEFI reference code
BUG=none
BRANCH=none
TEST=none
Change-Id: I69c3bd55f6340770402a67af2601e5df965b2b60
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 930577ac7b
Original-Change-Id: Icc9b27aaa14583d11d325e43d9165ddda72ca865
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20080
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531199
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Each I2C controller should have a unique pair of DMA request lines,
and DMA channels should be assigned incrementally, rolling over as
necessary.
Source: Intel Braswell UEFI reference code
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic4cffd5dce2387288f5b8559f497230b22ddce90
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f6cfa71217
Original-Change-Id: I1d97b5a07bf732c27caf57904c138b120b93ca81
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20079
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531198
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Use common init_igd_opregion method.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7b93ffe4853c129e3acc0126fb85fe8519d058ab
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9095e2f50e
Original-Change-Id: Ie70a49fd532b7ad7679dc558cc4a019a273a0602
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19906
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531197
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Copy Haswell's init_igd_opregion to common folder.
Remove platform specific code.
Will replace all Intel NB implementations.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3886dfb0c4a3c98cfb6c0c68a14852d88f0f5a8d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 96c3ef81fc
Original-Change-Id: I14dfb5986df264ffd71183a159f98b79e8e3230e
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19905
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531196
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Type 0x10 is mini RDIMM according to JEDEC DDR2 SPD
specifications.
BUG=none
BRANCH=none
TEST=none
Change-Id: I35c9634f36868caf03438e688c1ec5ab484c2449
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 87f7588c50
Original-Change-Id: I6d35bd74961326ebd9225f044313b107aca24bda
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20058
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/531195
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Commit 7c634ae8 (msrtool: added support for Intel CPUs) adds `no-pic` to
the compiler flags.
GCC 7.0.1 20170316 fails to built with the error below.
```
/usr/bin/ld: msrtool.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: msrutils.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: sys.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: linux.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: freebsd.o: relocation R_X86_64_32S against `.data' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: final link failed: Nonrepresentable section on output
```
Removing the flag causes the build to succeed with GCC 7, 6.3, and clang
4.0.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iba6a3ce9e098c60cf6ec6a6cd6d649df15486b91
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 459d2198eb
Original-Change-Id: I3d7aed27ce7f84aa27305c68e2d5f14607c58ec8
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18907
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Original-Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531194
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
For an unknown reason, the I2C ACPI devices were placed
under \SB intead of \SB.PCI0, as with all other non-Atom
based Intel platforms. While Linux is tolerant of this,
Windows is not. Correct by moving I2C ACPI devices where
they belong.
Also, adjust I2C devices at board level for intel/strago
and google/cyan as to not break compilation.
BUG=none
BRANCH=none
TEST=none
Change-Id: I39d845ba3b6d07d8bb5f63f663316750f03f20a6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6a67ffb6ea
Original-Change-Id: Iaf8211bd86d6261ee8c4d9c4262338f7fe19ef43
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20055
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531193
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibca733ea7c557899ff2f8d86362cccd7a41bbcca
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 397c7b3411
Original-Change-Id: Ie0b64eadc634049f6b65cf555407337fb7c4363c
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19976
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531192
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9f566b4c7117981e58709d3b8b52b410a5e3bbaf
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dc1b78130a
Original-Change-Id: I14ba3cea821e103208426e9fcaa0833d84157ff8
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19975
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531191
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Switch from lapic to tsc.
Allows timestamps to be used in coreboot, as there's a reference
clock available to calculate correct time units.
Clean Kconfig, remove duplicated lapic code and include tsc dir for
LGA1155 boards.
Tested on Lenovo T430.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4c179884707380e1417a251db8f70d0a915572af
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b9959e279c
Original-Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20044
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531190
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I0b3a475c1c875e51929e981d7a809f5e40b00e43
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 21e7424fc9
Original-Change-Id: I751e887bd90a258a69d13ea4ee9a409c8c86a3c3
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19591
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531189
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Update user facing camera i2c address to 0x36.
BUG=None
TEST=Build & boot on soraka. Make sure user facing camera is detected.
Change-Id: Id441041035e8a2962c859cac93d02858fc84d625
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5e10422df2
Original-Change-Id: I4645ae5734faef4b6a821c04ab817a7b99da6e4b
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20023
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/531188
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The RTC RX6110SA has several configuration options which might be
interesting to set. To make this setup independent of the driver itself
but let it still be configurable on mainboard level, add more
configuration options to the chip driver.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2050f013241e3ff6021ec1eb9aabf91f6d725229
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0dc405de98
Original-Change-Id: I7f8b2aa7cd001a887f271be36f655e10e60e778b
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/20084
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/531187
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
GCC version 7 is being a bit picky about pointer and integer comparison
by default, which triggers a crossgcc build error.
This backports a patch from upstream GCC to fix the issue.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie3424a428121ac8dead85707e691bd4d60e69183
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 37afb270b4
Original-Change-Id: I8b1e806c10604c0df080ac5edc667bf1141e2c17
Original-Signed-off-by: Paul Kocialkowki <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/20103
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531186
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the
reference clock can be 100Mhz.
Decode the register and use the reference clock to calculate
the selected DDR frequency.
Tested on Lenovo T430.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia5f46992e4d536a21922721eb97061a78e067e74
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6ab7e5e090
Original-Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19995
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/528271
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add additional ACPI opcodes, that are going to be used in the
following commits.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icc2d79902965feca18c5c502dffcd189329b4c44
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a038835716
Original-Change-Id: I20c3aa5a1412e5ef68831027137e9ed9e26ddbc9
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20087
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/528270
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fix regression introduced by commit 5c026445
(drivers/intel/wifi: Add support for generating SSDT table)
In case the regular PCI path is taken, there're no chip_ops and the code
will segfault. The bug was covered by other bugs that caused this code
to never execute.
Add NULL pointer checks and only fill in device name if one is provided.
Tested on Lenovo T430 and wifi card 8086:0085.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ieb95c7f281d8f69ecf3cc2e0e176a24923891a2f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6086b4ee38
Original-Change-Id: I84e804f033bcd3af1a7f76670275fdf5159d381f
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20082
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/528269
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
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