Commit graph

360 commits

Author SHA1 Message Date
Corey Osgood
fcf66e3605 Enable caching for Via C7 CPUs, and also improve readability. Tested on hardware
and seems to be working.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1164 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-04-14 15:41:33 +00:00
Ronald G. Minnich
5a90884bd4 last kontron commit.
This is a potentially good pointer to where someone can take this. 

While startup was working, BSP now explodes once the AP stops, while
BSP is doing startup IPI loop send #2. The code needs to be hardened; I 
think use of the shared variables would really make it much more solid. 
This would be a good undergrad student project if someone is looking for one.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1145 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-03-11 16:17:37 +00:00
Ronald G. Minnich
77407f5341 This is working up to the ljmpl to protected mode. It has all the
debugging in, using locations 0 and _secondary_start as POST. 

Calling from initram did not work out, as we have to disable_car in initram
to make such a call work (on core2). For now, 
I am calling this from stage1_phase 3, before stage2 is called. But that
has increased the code size of stage1, which is not a great idea. 

What I am thinking we ought to do: call this from stage2, before phase 1, 
so that CPUs are nice and set up and quiet. 
Provide phase2 with an SMP-safe printk. 

This is here so others may see it and correct my work. The good news is 
that SMP startup on core2 on v3 is now starting to go. But the better news
is that the way this is working is pretty generic and ought to apply to 
much more than just core2. 

To really look at object you might want to get ndisasm. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1143 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-03-05 05:48:43 +00:00
Ronald G. Minnich
52bdacea13 Again, this probably won't work but I want to make the code visible so
people can suggest what's wrong. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1139 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-24 03:38:37 +00:00
Ronald G. Minnich
509ab45a81 This is a trivial commit and I want to get other people to look at the code.
I can still get to linux but core1 is not working.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://coreboot.org/repository/coreboot-v3@1137 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-21 17:28:24 +00:00
Ronald G. Minnich
5f27d204bc This patch extends core2 smp support to v3. It is an
adaption of the v2 code, with significant cleanup and 
simplification. It also works in CAR mode, and has no .bss or .data
usage. It provides for a way to provide AP POST codes to the BSP. 

Since one common file with amd changed (lapic.h) I have build-tested this
against serengeti and it is fine.


It builds and I'll be testing it as soon as I can find the power supply for 
the kontron (it got "borrowed"). 
Index: arch/x86/intel/core2/init_cpus.c

new file. Basically an adaptation of the v2 code to v3. All global variables
removed. One big change to note: there is a stack struct, and the 
parameters to the secondary_start are struct members. Thus the BSP 
can watch the AP, and, neater, the AP can POST to a shared variable
and the BSP can see how far it got. 

Index: arch/x86/secondary.S
.S startup for AP. 
Index: arch/x86/Kconfig
Delete a dependency. 
Index: northbridge/intel/i945/reset_test.c
Add real cold boot detection. 

Index: mainboard/kontron/986lcd-m/Makefile
Add some new build files. 

Index: mainboard/kontron/986lcd-m/stage1.c

Get rid of ' in #warning that confused some tool. 

Index: mainboard/kontron/986lcd-m/initram.c
Call init_cpus. 

Index: mainboard/kontron/Kconfig
Turn off SMM for now. 

Index: include/arch/x86/lapic.h
Correct a static inline declaration. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://coreboot.org/repository/coreboot-v3@1136 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-21 00:05:20 +00:00
Ronald G. Minnich
41bb62d112 The initram build allows you to -fcombine the source. But if you put a
.S into the source file list, for reasons unknown, gcc only builds a .o 
with the .S symbols/code in it; all the .c bits disappear. 

So, a few changes:
1. add a rule for secondary.o, we're going to need it. 

I like the fact that adding a .S file is inconvenient. Good. 
Adding assembly should be hard. 

2. Make two steps to initram .o building: first, the .c files, then any 
    extra .o files as specified by the mainboard Makefile

I realize this is a bit ugly, if there is a better solution, I'll take it.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1135 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-19 23:50:38 +00:00
Ronald G. Minnich
2fe48ba7d5 Add this file from v2. Not build tested, just want to get it in.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1134 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-18 21:17:22 +00:00
Marc Jones
b6c89edb04 Improve the setup of MTRRs in stage1 to handle alignment and power of
2 size calculations.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1133 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-15 18:12:34 +00:00
Myles Watson
9d6d811dd1 This patch converts __FUNCTION__ to __func__, since __func__ is standard.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1131 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-12 21:15:34 +00:00
Marc Jones
f2872767a2 Add AP detection to stage0 to prevent APs from re-initializing mainboard setup
that has already been done by the BSP. For single processor systems the CPU
flag is always 0, BSP. This code also moves the AP stop for K8 mainboards to
after memory setup so the AP's MTRRs can be setup to match system memory.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1129 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-10 22:41:35 +00:00
Marc Jones
a794edb17b Setup the MTRRs in stage1 so that memory and cache are available throughout
stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
It also sets all system memory to WriteBack cached and sets the ROM
area to cached.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1128 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-10 22:40:10 +00:00
Marc Jones
333cdb149f Coreboot uses the compiler option -mregparm=3 which causes variables to
be passed in registers. This is good for size and speed but not good when
we call a C function from asm. Force stage1_phase1 to use stdcall and get
variables off the stack.

Note that I didn't change stage1_phase3 because it doesn't use any 
variables.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1127 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-10 22:35:49 +00:00
Mart Raudsepp
2d5920e5ba Remove unused pciconf.h header with constants that everyone uses by value instead per convention
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1110 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-08 17:21:37 +00:00
Myles Watson
f59b4ca24a This patch removes the offset_pciio since there is never an offset_pciio an
offset_pciio and an offset_io.  This makes it easier to port things from v2.

It also updates mcp55 and some whitespace there.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1099 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-05 23:04:13 +00:00
Corey Osgood
034ea33797 Fix breakage of k8 targets caused by r1085. Thanks to Myles Watson for
tracking down the offending commit.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1088 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-30 07:02:52 +00:00
Corey Osgood
305d400a83 This patch fixes a few small problems and gets cn700 to read from an IDE
disk and attempt to boot a linux kernel.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1087 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-23 23:44:39 +00:00
Ronald G. Minnich
a492ff7cc9 Kill off stage1_mtrr.c completely, and bring in mtrr.c for stage2 from v2.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>

It could use some cleanup, but looks good.

Acked-by: Peter Stuge <peter@stuge.se>

With some cleanup.

Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://coreboot.org/repository/coreboot-v3@1085 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-23 19:02:44 +00:00
Ronald G. Minnich
4697e91e08 This is an emergency fix for the kontron. This fix now allows us to boot to
etherboot. 

The fix is to replace the wbinvd with an invd. The wbinvd is a bad idea, 
since the cache at this point is full of tags to a location that is not backed 
by memory. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1084 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-23 07:09:46 +00:00
Corey Osgood
758fecb860 Move OPTION_TABLE to a menu config option, and default it to enabled. This allows
a user/developer to disable the option table, so it doesn't overwrite whatever
the factory BIOS has written. Also fix building with OPTION_TABLE disabled.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1078 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-18 02:00:55 +00:00
Corey Osgood
4216c13386 Make C7/CN700 boot to memtest86, and pass that test. Booting is very slow, ~15min to get to a memtest
payload.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1077 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-17 21:17:01 +00:00
Myles Watson
80aa586a51 Subject: [PATCH 4/5] integration of biosemu (aka YABEL) into coreboot
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1076 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-16 22:46:55 +00:00
Carl-Daniel Hailfinger
e4d46b9e90 early_mtrr_init() nukes all MTRRs including those which we use for CAR.
That means if it ever gets called while CAR is active, our stack will be
dropped and mayhem will ensue.
Besides that, it just replicated stage0.S functionality which already
nukes all MTRRs before enabling CAR.

We could move XIP ROM caching from stage0.S to early_mtrr_init(). It
would probably slow down booting a bit, but the amount of asm code would
be reduced.

Thanks to Corey for telling me that early_mtrr_init() broke booting for
him.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1067 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-10 18:34:16 +00:00
Ronald G. Minnich
f7a5eaf57e Add support for creating an smm top-level object.
Whether SMM is added or not depends on the mainboard. To enable SMM, 
the Kconfig variable SMM should be set, and the SMM variable should be 
defined in the mainbard. 

Also correct a type CONFIG_HPET should be HPET. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1065 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-06 03:59:24 +00:00
Carl-Daniel Hailfinger
db67cc9a61 Document unexpected clobbering of stage0 code.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1064 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-03 23:39:49 +00:00
Carl-Daniel Hailfinger
eb09a75c49 Fix a missing dependency on arch/x86/stage0_common.S (that's an included
file from all arch/x86/*/stage0.S).

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1062 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-03 02:14:30 +00:00
Stefan Reinauer
8e7ca90b6f back out until this issue is really fixed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1059 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-26 09:17:29 +00:00
Carl-Daniel Hailfinger
645bd273e1 Experimental backout of the critical code parts in r1057 as requested
by Stefan.
The only changes left from r1057 are:
- Added comments
- Two initial pushes of 0x00000000 (32 bits each) to the stack as safety

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1058 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-26 02:16:37 +00:00
Carl-Daniel Hailfinger
5a6f83c735 The Core2Duo CAR code did set up the stack incorrectly. In combination
with a wrong calling convention of stage1_phase1() this caused stage1 to
assume BIST had failed.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1057 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-25 23:39:31 +00:00
Stefan Reinauer
675731bf42 hack to make v3 rom access a lot faster.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1056 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-25 23:10:24 +00:00
Stefan Reinauer
20e53b2345 get into ram init on kontron board.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1055 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-25 22:51:15 +00:00
Carl-Daniel Hailfinger
0153293887 Not a single file is being rebuilt in v3 if build.h changes. That means
the console banner and the option table will never be updated with more
recent build.h strings.

Thanks to Mart Raudsepp for spotting this oddness.

x86emu doesn't care about the contents of build.h, it just uses build.h
to check whether it is compiled in conjunction with coreboot.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1036 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-16 22:59:52 +00:00
Myles Watson
b875333abf This patch makes it so serengeti builds again.
It includes an ide option that has to be there, and fixes a CPU test in
Kconfig.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1021 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 15:19:39 +00:00
Ronald G. Minnich
5a205b9067 Add core2 stage1.c dependency
Index: arch/x86/intel/core2/stage1.c
Initial core2 disable_car and stop_ap
disable_car is wrong but we can fix that tomorrow -- it's core 2 day on friday!

Index: arch/x86/via/stage1.c
Add empty stop_ap()

Index: mainboard/kontron/986lcd-m/stage1_debug.c
Cleanup
Index: mainboard/kontron/986lcd-m/initram.c
Cleanup
Index: mainboard/jetway/j7f2/stage1.c
Remove definition of stop_ap; this belongs in the cpu!
Index: southbridge/intel/i82801gx/libsmbus.c
Fix definition of TIMEOUT (i.e. remove it)

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1019 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 05:05:24 +00:00
Carl-Daniel Hailfinger
99e68b9345 Kill v2 leftovers.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1013 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-13 01:53:55 +00:00
Carl-Daniel Hailfinger
cb9db3b6d0 We are woefully unaware about how much stack v3 really uses.
This is a complete rewrite of my earlier stack checker proposal.
It works for CAR and RAM, has better abstraction and actually gives us
nice results.
The stack checker is default off due to its rather measurable impact on
boot speed.
Diagnostic messages are printed on first initialization, directly after
RAM init and directly before passing control to the payload. Sample qemu
log is attached. Extract from that log follows:

coreboot-3.0.986 Fri Nov  7 04:04:37 CET 2008 starting...
(console_loglevel=8)
Initial lowest stack is 0x0008fe98
Choosing fallback boot.
[...]
Done RAM init code
After RAM init, lowest stack is 0x0008fe30
Done printk() buffer move
[...]
LAR: load_file_segments: Failed for normal/payload
Before handoff to payload, lowest stack is 0x0008bf50
FATAL: No usable payload found.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1012 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-13 01:28:32 +00:00
Carl-Daniel Hailfinger
fbff7d2fd0 The VIA C7 CAR disable code in v3 had a nasty bug which caused the
processor to reset. Fix this bug and actually disable CAR.
With this patch v3 has better C7 CAR code than v2 (which skips two key
MTRRs).

Thanks to Corey Osgood for testing countless debug patches.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1010 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-13 00:04:55 +00:00
Ronald G. Minnich
f37c28c24b I'm committing often as I don't want people to run over each other (and I am waiting on BlueGene to schedule me
and keep getting called away ... waiting for 1024 procs takes patience!)

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1008 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-12 22:43:50 +00:00
Stefan Reinauer
4b9385ae89 initial intel core car code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1002 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-12 14:12:32 +00:00
Ronald G. Minnich
50403f09b2 Filling in core 2 support.
This actually starts to get compile errors, instead of config errors. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@994 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-12 00:38:13 +00:00
Carl-Daniel Hailfinger
4a03ab07aa initram is linked with very special options to ld. It is not immediately
obvious that they are needed, so a comment to that effect will hopefully
prevent accidental "cleanups" in the future when nobody remembers the
history of that makefile rule anymore.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@988 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-08 22:39:35 +00:00
Myles Watson
2b105d9bee This patch removes code related to PCI type 2 configuration cycles (gone as of
PCI 2.2)

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@982 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-05 22:18:53 +00:00
Marc Jones
f77a0a29b1 Update K8 FID/VID setup to match coreboot v2. Add support for 100MHz FIDs
(revG).

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@979 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-04 17:00:07 +00:00
Carl-Daniel Hailfinger
4213668ab5 Once we touch the MTRRs in VIA disable_car(), the CPU resets. Since
workarounds are better than instant reboots, mangle the code so that it
only switches stacks and flushes the cache.

There are two genuine fix in there as well:
We have to switch %esp before CAR is disabled. That way, the stack is
always valid.
And one of the nastier bugs easily happening in C: We had a pointer to a
const struct, but we wanted a const pointer to a struct. This kills the
(correct) warning about that code.

Many thanks to Corey for testing countless iterations of that code.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested and
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@978 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-02 14:47:21 +00:00
Ronald G. Minnich
4964e25101 Get via to use standard mtrr init functions. Start to document them.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://coreboot.org/repository/coreboot-v3@976 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-01 00:53:01 +00:00
Ronald G. Minnich
4f2df501f9 no PIRQ table
Make cmos.layout work with incomprehensible tool -- just turn off checksums.
Add static.c to list of files covered by kscope

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@975 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-31 22:43:02 +00:00
Ronald G. Minnich
cfa4c50225 This is the beginning of support for saving base registers that already have a v
alue. There 
is a known bug in v2/v3 wherein a BAR that is set is ignored. This change will c
ome in very
slowly as it is a bit tricky to get right as we redesign the dev code.

Also make the vm86 stuff use the SRC instead of OBJ names so we can see it in ks
cope. 

Finally, beginnings of documentation changes, not finished yet. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@965 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-31 17:40:01 +00:00
Myles Watson
81b32098c1 This patch clears up a few warnings in stage1 code. It removes an unused variable, moves a declaration into an ifdef, and adds a cast.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@959 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-29 02:19:42 +00:00
Myles Watson
e7ea68860d Trivial fixes of printk \r\n and white space.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@958 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-28 17:29:07 +00:00
Uwe Hermann
9b90a6f22b Fix a bunch of Doxygen warnings in v3 (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@951 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-23 18:55:01 +00:00