Emulation/switch-coreboot
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Again, this probably won't work but I want to make the code visible so

Browse source 
people can suggest what's wrong. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1139 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2009-02-24 03:38:37 +00:00
parent bee5429ba6
commit 52bdacea13
2 changed files with 6 additions and 5 deletions
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4
arch/x86/intel/core2/init_cpus.c
View file

@ -287,7 +287,7 @@ static int lapic_start_cpu(unsigned long apicid, u32 *secondary_base)
/* Boot on the stack */
/* Kick the second */
printk(BIOS_SPEW, "Send start_eip %#lx(%#lx)\n", start_eip, start_eip>>12);
printk(BIOS_SPEW, "Send start_eip %#lx(%#lx) sb[-1] %p\n", start_eip, start_eip>>12, (void *) secondary_base[-1]);
lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP
| (start_eip >> 12));
@ -321,7 +321,7 @@ static int lapic_start_cpu(unsigned long apicid, u32 *secondary_base)
if (send_status || accept_status)
break;
}
printk(BIOS_SPEW, "After Startup.\n");
printk(BIOS_SPEW, "After Startup.sb[-1] %p\n", (void *) secondary_base[-1]);
if (send_status)
printk(BIOS_WARNING, "APIC never delivered???\n");
if (accept_status)

7
arch/x86/secondary.S
View file

@ -24,12 +24,13 @@
.text
.globl _secondary_start, _secondary_start_end
_secondary_start:
1:
.code16
.balign 4096
cli
movl $1b, %ebx
xorl %eax, %eax
movl %eax, %cr3 /* Invalidate TLB*/
/* On hyper threaded cpus, invalidating the cache here is
* very very bad. Don't.
*/
@ -60,8 +61,8 @@ secondary32:
lidt idtarg
/* Set the stack pointer */
movl $_secondary_start-4,%eax
movl 0x0(%eax),%esp
movl -4(%ebx),%esp
movl $0, -4(%ebx)
call secondary_cpu_init
1: hlt