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switch-coreboot/arch/x86
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Marc Jones a794edb17b Setup the MTRRs in stage1 so that memory and cache are available throughout 
stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
It also sets all system memory to WriteBack cached and sets the ROM
area to cached.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1128 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-10 22:40:10 +00:00
..
amd Setup the MTRRs in stage1 so that memory and cache are available throughout 2009-02-10 22:40:10 +00:00
geodelx Right now we face the problem that we can't support processors which 2008-10-16 03:00:28 +00:00
i586 Right now we face the problem that we can't support processors which 2008-10-16 03:00:28 +00:00
intel/core2 This is an emergency fix for the kontron. This fix now allows us to boot to 2008-12-23 07:09:46 +00:00
via This patch fixes a few small problems and gets cn700 to read from an IDE 2008-12-23 23:44:39 +00:00
archelfboot.c Move include/console/console.h to include/console.h in order to 2007-05-05 20:18:28 +00:00
archtables.c This patch adds explicit casts to remove some compiler warnings. 2008-10-23 16:47:42 +00:00
coreboot_table.c Not a single file is being rebuilt in v3 if build.h changes. That means 2008-11-16 22:59:52 +00:00
i8259.c Now version 3: LinuxBIOS -> coreboot rename. 2008-01-27 18:54:57 +00:00
isa-dma.c Ron's arch code., slightly changed. Another one will follow 2007-06-27 21:01:01 +00:00
Kconfig Kill off stage1_mtrr.c completely, and bring in mtrr.c for stage2 from v2. 2008-12-23 19:02:44 +00:00
keyboard.c The current parameter situation of post_code() is rather mixed between 2008-01-07 16:34:34 +00:00
ldscript.ld Cover for unknown strange thing that just happened in svn. 2008-10-06 23:20:41 +00:00
Makefile Kill off stage1_mtrr.c completely, and bring in mtrr.c for stage2 from v2. 2008-12-23 19:02:44 +00:00
mc146818rtc.c Move OPTION_TABLE to a menu config option, and default it to enabled. This allows 2008-12-18 02:00:55 +00:00
mtrr.c Kill off stage1_mtrr.c completely, and bring in mtrr.c for stage2 from v2. 2008-12-23 19:02:44 +00:00
multiboot.c This patch adds explicit casts to remove some compiler warnings. 2008-10-23 16:47:42 +00:00
pci_ops_auto.c Remove unused pciconf.h header with constants that everyone uses by value instead per convention 2009-01-08 17:21:37 +00:00
pci_ops_conf1.c Remove unused pciconf.h header with constants that everyone uses by value instead per convention 2009-01-08 17:21:37 +00:00
pci_ops_mmconf.c Remove unused pciconf.h header with constants that everyone uses by value instead per convention 2009-01-08 17:21:37 +00:00
pirq_routing.c Minor cosmetic and/or license header fixes (trivial). 2008-08-11 21:01:54 +00:00
post_code.c Now version 3: LinuxBIOS -> coreboot rename. 2008-01-27 18:54:57 +00:00
resourcemap.c This patch removes the offset_pciio since there is never an offset_pciio an 2009-01-05 23:04:13 +00:00
serial.c Now version 3: LinuxBIOS -> coreboot rename. 2008-01-27 18:54:57 +00:00
speaker.c Remove superfluous checks for boolean CONFIG_* variables where we tested 2008-02-14 22:34:40 +00:00
stage0_common.S Document unexpected clobbering of stage0 code. 2008-12-03 23:39:49 +00:00
stage1.c Coreboot uses the compiler option -mregparm=3 which causes variables to 2009-02-10 22:35:49 +00:00
stage1_mtrr.c Setup the MTRRs in stage1 so that memory and cache are available throughout 2009-02-10 22:40:10 +00:00
udelay_io.c Now version 3: LinuxBIOS -> coreboot rename. 2008-01-27 18:54:57 +00:00