Setting both bits 27 and 7 of PCH register PMSYNC_CFG (PMSYNC
Configuration; offset 0x33c8) causes pre-OS display init to fail
on HSW-U/Lynxpoint and BDW-U ChromeOS devices when the VBIOS/GOP
driver is run after the register is set. A re-examination of
Intel's reference code reveals that bit 7 should be set for the
LP PCH, and bit 27 for non-LP, but not both simultaneously.
The previous workaround was to disable the entire power optimizer
section via a Kconfig option, which isn't ideal.
Test: unset bit 27 of PMSYNC_CFG and boot google/lulu,
observe functional pre-OS video output
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie0cc1b294a4f8722bdd3a79faef1516f503d2e03
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c97e042a9b
Original-Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18385
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445153
We've been able to narrow down the problem to a single register/
single bit, so revert this commit and address the problem in a
follow-on commit.
This reverts commit 0f2025da0f.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0e986e2be69c6e74eb57c70b13cf625b0317c44d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ee6a612eb2
Original-Change-Id: I780f9ea2976dd223aaa3e060aef6e1af8012c346
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18384
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445152
It explains the prerequisites to run the script, some
background on how to setup the computer running the script,
and the board it gathers the information from.
That information is too long to fit inside the script's
help.
BUG=none
BRANCH=none
TEST=none
Change-Id: I140c19404433fbeb457a349f39ce26efbb312d13
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: efd9dee646
Original-Change-Id: Iecba7310ff1583149c02728e955716775bcbbdc4
Original-Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Original-Reviewed-on: https://review.coreboot.org/6660
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445151
Add a test in case we have a DIMM2 not populated but DIMM3 is.
BUG=none
BRANCH=none
TEST=none
Change-Id: I80508fd652795593aef7e202891b494d60d4d6a9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 75da1fb2ba
Original-Change-Id: I14f82afe03884740570838e7b2771233356c518d
Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Original-Reviewed-on: https://review.coreboot.org/18386
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/445150
Coverity is detecting 'sp' as a variable which has not been initialized.
This is obviously not correct, so this patch *TRIES* to mark it as false
I'm not positive that this will work because the annotation needs to go
on the line above the error, but this error is inside of a # define.
Does the whole #define count as one line? Can it go on the line
above the #define in the .h file? Does it have to precede every line
where the #define is used? The documentation doesn't make this clear.
Should suppress coverity issues: 1368525 & 1368527
uninit_use: Using uninitialized value sp.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8fa056af3e829218d8139f3899b7291e62ea6796
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f797a1ac6a
Original-Change-Id: Ibae5e206c4ff47991ea8a11b6b59972b24b71796
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18247
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://chromium-review.googlesource.com/445149
The hybrid driver select by DRIVERS_LENOVO_HYBRID_GRAPHICS doesn't work
for t400/t500.
Replace it with a custom romstage implementation.
Tested on Lenovo T500 with dual graphics:
* Intel Native GFX init
* AMD VBios
* GNU Linux 4.8.13
* SeaBios as payload
* Discrete is working (44 W)
* Integrated is working (24 W)
* Switchable is working (34 W)
** Both GPUs are enabled, with Intel being connected to the panel
** DRI_PRIME allows to use AMD GPU
** ACPI doesn't seem to work (no vgaswitcheroo)
Depends on Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422
Depends on Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201
BUG=none
BRANCH=none
TEST=none
Change-Id: I8319fb3c52c32b548820f49dea0aee53b8e509d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f9d5308690
Original-Change-Id: I7496876e9b434d4a2388e1ede27ac604670339b7
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18010
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/445147
This company doesn't do custom hardware anymore and doesn't
host the sources anymore. We therefore point to the archived
sources instead.
BUG=none
BRANCH=none
TEST=none
Change-Id: I666ce3aafcaa82e64b7945f1489097b04e0a6b98
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 418e808fa6
Original-Change-Id: I5ce4f6a468b852fc1d0947fe2b28a5297f14c437
Original-Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Original-Reviewed-on: https://review.coreboot.org/11889
Original-Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/445145
It rewrites the results of receive enable stored in the upper nvram
region, to avoid running receive enable again.
Some debug info is also printed about the self-refresh registers.
(Not enforcing a reset here, since 0 does not necessarily mean it's
not in self-refresh).
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie8a85069cc613706c1405e150bece11bc6ba43c1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ef7e98a2ac
Original-Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17998
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445144
Previously the raminit failed on hot reset and to work around this
issue it unconditionally did a cold reset.
This has the following issues:
* it's slow;
* when the OS issues a hot reset some disk drives expect their 5V
power supply to remain on, which gets cut off by a cold reset,
causing data corruption.
To fix this some steps in raminit must be ommited on the reset path.
This includes receive enable calibration.
To achieve this it stores receive enable results in RTC nvram for them
to be rewritten on the resume path.
Note: The same thing needs to be done on the S3 resume path.
Calling a hot reset after raminit "outb(0x6, 0cf9)" works.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7abad55524ecea8bbd828aba6dd3ce7708f1a7bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97e13d84c3
Original-Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18009
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/445143
Configure GRUB to build with boot time statistics. That allows users
to add that module to GRUB by adding `boottime` to the list of extra
modules.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iab5d114c243119bd539ef2aec1efacd2eacd2f58
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7c7b176169
Original-Change-Id: I76a07e49aecb37652fe8c7d6a9421fd464424287
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18367
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/445142
Some simple implementation of the MultiBoot protocol may not pass a
memory map (MULTIBOOT_FLAGS_MMAP missing in the flags) but just the two
values for low and high memory, indicated by the MULTIBOOT_FLAGS_MEMINFO
flag.
Support those kind of boot loaders too, instead of falling back to the
hard-coded values in lib_get_sysinfo().
Tested with a multiboot enhanced version of FILO.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4c1d95a8f4aa8735538dad85d5f856ce36a5f72e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 898de6111a
Original-Change-Id: I22cf9e3ec0075aff040390bd177c5cd22d439b81
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18350
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/445141
Maxim 98927 kernel driver requires entries in the ACPI SSDT table,
add a SSDT generator as part of this driver.
BUG=chrome-os-partner:62051
BRANCH=None
TEST=After boot, dump and verify that the generated SSDT ACPI table has the
required entries.
Change-Id: I9043f9f0b66b45d04e8b8cbe8c99b77686fd5666
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4979d7610e
Original-Change-Id: Ic2d4d8449288bc00d085852220b2e1e7a208e9ef
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: M Naveen <naveen.m@intel.com>
Original-Signed-off-by: Dylan Reid <dgreid@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18211
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445127
Currently there is no distinction between mainboards using
Skylake or Kabylake SoC, Add a config option for Kabylake
SoC to allow mainboards to explicitly select if they are
using it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1c0e5acebce9db7e06e2e320dbdf67d6c63061b7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0700dca969
Original-Change-Id: Ie7960bd81f88a223894afe3115ddc0bc637e4be4
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18312
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445124
There are MSRs that are programmable per-core not per-thread, so add
a function to check whether current executing CPU is a primary core
or a "hyperthreaded"/secondary core. For instance when trying to
program Core PRMRR MSRs(per-core) with mp_init, cpu exception is thrown
from the secondary thread. This function was used to avoid that.
Potentially this function can be put to common code or arch/x86 or cpu/x86.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified core PRMRR MSRs get programmed only on primary
thread avoiding exeception.
Change-Id: I6d837f50db404f35606f1f975b05456946605c10
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 2b194d9741
Original-Change-Id: Ic9648351fadf912164a39206788859baf3e5c173
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18366
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444818
Implement the argc/argv passing as described in coreboots payload API:
http://www.coreboot.org/Payload_API
While at it, give the code some love by not needlessly trashing register
values.
BUG=none
BRANCH=none
TEST=none
Change-Id: If49874b1ac1c7359816f4ec02c5380c32101fa1a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: d2f16cac74
Original-Change-Id: Ib830f2c67b631b7216843203cefd55d9bb780d83
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18336
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/444817
Simplify the code by directly using the arguments on the stack as base
pointer relative memory references, instead of loading them into
intermediate registers first.
Make it more robust by preserving all callee saved registers mandated by
the C calling convention (and only those), namely EBP, EBX, ESI and EDI.
Don't assume anything about the register state when the called function
returns -- beside the segment registers and the stack pointer to be
still the same as before the call.
BUG=none
BRANCH=none
TEST=none
Change-Id: I231828bb9a65a6b1077b17024c0c59fed8546284
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 57dc93c967
Original-Change-Id: I383d6ccefc5b3d5cca37a1c9b638c231bbc48aa8
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18335
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/444816
According to coreboots payload API [1], the called payload should be
able to return a value via %eax. Support this by changing the prototype
of start_main() and pass on the return value of main() to the caller
instead of discarding it.
[1] https://www.coreboot.org/Payload_API
BUG=none
BRANCH=none
TEST=none
Change-Id: I1782c45b615d431de8be5a533d5890ed53ddb9d8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 7b681c5926
Original-Change-Id: I8442faea19cc8e04487092f8e61aa4e5cba3ba76
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18334
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444815
According to coreboots payload API [1] the argc value should be passed
at stack offset 0x10, so we need to push a dummy value to comply to the
API.
[1] https://www.coreboot.org/Payload_API
BUG=none
BRANCH=none
TEST=none
Change-Id: I2acc66d20fcc4e313d1ddbc4a7bc1772548981c5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 9fa78c136d
Original-Change-Id: Id20424185a5bf7e4d94de1886a2cece3f3968371
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18333
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444814
scan_smbus routine does not perform any smbus specific operation. Thus,
rename the routine to scan_generic_bus so that it can be used by other
buses like SPI. Add a wrapper scan_smbus to allow other users of smbus
scan to continue working as before.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: Id2b6342d96915e47c265c7984f651680632a3903
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 4e08479688
Original-Change-Id: I8ca1a2b7f2906d186ec39e9223ce18b8a1f27196
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18363
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/444809
Add support for a new "SPI" device type in the devicetree to bind a
device on the SPI bus. Allow device to provide chip select number for
the device as a parameter.
Add spi_bus_operations with operation dev_to_bus which allows SoCs to
define a translation method for converting "struct device" into a unique
SPI bus number.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.
Change-Id: Id5ef64e11a862f4075afa06a7eca25bfc84fc9aa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 7606c377f5
Original-Change-Id: I86f09516d3cddd619fef23a4659c9e4eadbcf3fa
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18340
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/444808
Update sconfig lex and yacc files to add support for a new "SPI" device
type in the devicetree. SPI device takes only parameter i.e. chip select
number for the device on the SPI bus.
Re-generate the shipped files for sconfig using flex 2.6.0 and bison
3.0.4 (make CONFIG_SCONFIG_GENPARSER=1). Clean up local paths that leak
into generated files.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.
Change-Id: If1595a4b6c5a3902f04dd0270a927c3dd418db48
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: e67002968b
Original-Change-Id: If0831e25b3e4ed87827ad92356d7bf47b6387884
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18339
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444807
The pointer to write the return value to is in %ecx, not %eax. Writing
to (%eax) leads to memory corruptions as %eax holds the return value,
e.g. would write zero to address zero for a "successful" returning
payload.
BUG=none
BRANCH=none
TEST=none
Change-Id: I92d9ceec19d236e756c4eaf2ecf9c0534a3ad482
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 901efea8ab
Original-Change-Id: I82df27ae89a9e3d25f479ebdda2b50ea57565459
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18332
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/443927
This commit makes a basic adjustment for GPIOs, device tree, flash map and
MRC settings. With these basic settings the mainboard boots into
Linux lubuntu 4.8.0-22-generic using SeaBIOS. More adjustments will follow.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic79be51b2d99ebbc2629e19f6110ad10f12028ab
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 6abdbcd4dc
Original-Change-Id: Ia920d236814f2e6a9b777dd1e4b4feef0ddf7721
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/18292
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/443925
The four options are only used in X86:
- BOOTBLOCK_SIMPLE
- BOOTBLOCK_NORMAL
- BOOTBLOCK_SOURCE
- SKIP_MAX_REBOOT_CNT_CLEAR
Move them all into src/arch/x86/Kconfig - this puts them in the chipset
menu instead of general setup.
Verified that this makes no significant changes to any config file.
BUG=none
BRANCH=none
TEST=none
Change-Id: If9a61ed8a0b9add3b4f70dfb15ea0213c452f584
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 408fda799a
Original-Change-Id: I2798ef67a8c6aed5afac34322be15fdf0c794059
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17909
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/443682
For boolean types, 'n' is the default default value - it doesn't
NEED to be set. If it IS set, it prevents a later default from
being set. So by removing the 'default n' statements from the
early symbols, they can be overridden other places in the tree.
Verified that this makes no significant changes to any config file.
BUG=none
BRANCH=none
TEST=none
Change-Id: If1d6e0be8feb731f073b7b3815504e6cd1957976
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: c8d16f4933
Original-Change-Id: I1b5b66bd8a3df8154a348b5272c56c88829b3ab4
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17908
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/443681
Some variants need the internal pull resistor on GPIO_SSUS_40
set explicitly to pull down rather than disabling the pull,
in order for the ram-id to be read correctly via GPIO.
Correct this by adding a function to enable and set the internal pull
and define its use as needed in the board's variant.h.
Chromium source:
branch: firmware-gnawty-5216.239.B
/src/soc/intel/baytrail/baytrail/gpio.h#418
/src/mainboard/google/gnawty/romstage.c#60
Test: boot 4GB Candy board and observe correct RAM id, amount detected
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia648846f4cdf65908db9a310b201562f0ff72951
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 474a7c51ce
Original-Change-Id: I8823c27385f4422184b5afa57f6048f7ff2a25ab
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18309
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/443676
Those are the result from tracing what linux or the option rom do
but are not needed here.
TESTED on Thinkpad X60.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4aa3ebf50bc772ff0baf0b6c685022ea40750234
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: d81078d944
Original-Change-Id: I4297a78c4ab6a19ef6161778c993fc3f3fb08c7e
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18294
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/443675
Kernel relies on FADT 8042 flag to enable/disable
8042 interface. If FADT reports 8042 capability and
8042 (/PS2) capability is actually disabled by coreboot,
kernel would assume the presence of 8042 based on the
FADT flag. This results in undesired system power off when
kernel tries to access the 8042 memory region. To address
this, CONFIG_NO_FADT_8042 was added to selectively
disable 8042 on FADT.
BUG=chrome-os-partner:61858
TEST=Boot OS and verify FADT 8042 flag
Change-Id: I45e667950850209b33531dbb7ed784f073648e69
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 2864f85725
Original-Change-Id: Ic80b3835cb5cccdde1203e24a58e28746b0196fc
Original-Signed-off-by: Jenny TC <jenny.tc@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18307
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/443672
Commit-Ready: Jenny Tc <jenny.tc@intel.com>
According to USB 2.0 Spec Table 7-7, the High-speed squelch
detection threshold Min 100mV and Max 150mV, and we set USB
2.0 PHY0 and PHY1 squelch detection threshold to 150mV by
default, so if the amplitude of differential voltage envelope
is < 150 mV, the USB 2.0 PHYs envelope detector will indicate
it as squelch.
On Kevin board, if we connect usb device with Samsung U2 cable,
we can see that the impedance of U2 cable is too big according
to the eye-diagram test report, and this cause serious signal
attenuation at the end of receiver, the amplitude of differential
voltage falls below 150mV.
This patch aims to reduce the PHY0 and PHY1 otg-ports squelch
detection threshold to 125mV (host-ports still use 150mV by
default), this is helpful to increase USB 2.0 PHY compatibility.
BRANCH=gru
BUG=chrome-os-partner:62320
TEST=Plug Samsung U2 cable + SEC P3 HDD 500GB/Galaxy S3 into
Type-C port, check if the USB device can be detected.
Change-Id: Ib20772f8fc2484d34c69f5938818aaa81ded7ed8
Signed-off-by: William wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/431015
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Inno Park <ih.yoo.park@samsung.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
