UPSTREAM: intel/skylake: add function is_secondary_thread()

There are MSRs that are programmable per-core not per-thread, so add
a function to check whether current executing CPU is a primary core
or a "hyperthreaded"/secondary core. For instance when trying to
program Core PRMRR MSRs(per-core) with mp_init, cpu exception is thrown
from the secondary thread. This function was used to avoid that.

Potentially this function can be put to common code or arch/x86 or cpu/x86.

BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified core PRMRR MSRs get programmed only on primary
thread avoiding exeception.

Change-Id: I6d837f50db404f35606f1f975b05456946605c10
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 2b194d9741
Original-Change-Id: Ic9648351fadf912164a39206788859baf3e5c173
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18366
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444818

src/soc/intel/skylake/cpu.c

@@ -435,6 +435,17 @@ static int adjust_apic_id(int index, int apic_id)
 		return index;
 }
 
+/* Check whether the current CPU is the sibling hyperthread. */
+int is_secondary_thread(void)
+{
+	int apic_id;
+	apic_id = lapicid();
+
+	if (!ht_disabled && (apic_id & 1))
+		return 1;
+	return 0;
+}
+
 static void per_cpu_smm_trigger(void)
 {
 	/* Relocate the SMM handler. */

src/soc/intel/skylake/include/soc/cpu.h

@@ -67,5 +67,6 @@ int cpu_config_tdp_levels(void);
 u32 cpu_family_model(void);
 u32 cpu_stepping(void);
 int cpu_is_ult(void);
+int is_secondary_thread(void);
 
 #endif