Commit graph

52 commits

Author SHA1 Message Date
Carl-Daniel Hailfinger
07f3009f43 Introduce a generic global variable storage mechanism and switch the
printk buffer management to it.

Build tested and boot tested and result tested on Qemu.

Adding a new global variable is not as easy as it looks, but the
comments in the code should be good enough to tell you how.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@760 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-14 09:25:58 +00:00
Ronald G. Minnich
7e78ce492a Make some things (die, mem*, resourcemap code, option code) SHARED.
The option code is tricky as it is used by standalone code. If you 
include that file and you are standalone, you now have to define 
STANDALONE (is there a better way?)
Change the cpuid to be a 24-byte string instead of 3 u32s.
Make the CPUID usage PIC-safe by not using %ebx.

Test building on two different geodes, tested to boot on dbe62

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@750 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-12 03:39:39 +00:00
Ronald G. Minnich
8a10a0e683 Add lapic defines and support.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@745 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-11 23:02:34 +00:00
Uwe Hermann
9eb8578b75 Minor cosmetic and/or license header fixes (trivial).
This includes using consistent (C) lines, adding email addresses,
and so on. The file southbridge/nvidia/mcp55/dts was never edited
by Yinghai Lu (thus removing his (C) line) and would be too trivial
anyway...

The changes (though trivial) were also informally acked by Ron on IRC.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>




git-svn-id: svn://coreboot.org/repository/coreboot-v3@744 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-11 21:01:54 +00:00
Ronald G. Minnich
120f4203a9 Add needed defines for k8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@732 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-10 22:02:15 +00:00
Ronald G. Minnich
649c9f99ff Console:
(1)we now compile in all printks, which is good: we can print any message provided we can change
the console log level at any time. 
(2) The console log level is compiled in and unchangeable, which is bad, as it defeats the purpose of (1).

Add a BIOS_ALWAYS log level. Make console log level a variable. Make functions that set it and get it
visible everywhere. Always print out the version message; this is really *not* noise!

PCI: Simplify pci functions so that they can be used in stage1 or anywhere for that matter. Add
a find function which is needed for many stage1 functions. Note that we copy but also clean up
the libpayload stuff just a bit. 

Get rid of config space type 2. If there was ever a platform that used it, I don't know what it was, 
and the presence is a needless distraction. 

tested and working on DBE62 (which means the console and the pci functions work :-).

There is a remaining problem with dumplxmsrs which nobody understands. It prints out garbage if we use the 
%s for the msr names. 

Formatting is an issue; if somebody wants to fix formatting they can assume I will ack it. Sorry, 
my emacs has gone just nuts. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@729 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-09 21:03:57 +00:00
Ronald G. Minnich
da9286b479 State of the tree for K8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@722 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-05 02:48:54 +00:00
Ronald G. Minnich
54b7a9609f With a bug fix from peter and a suggest change by Carl-Daniel
Resource map and a way to use the pci config stuff from stage 1, done in 
a way that will work in stage 2 (but only for systems that use type 1
config cycles; will fail for type MEM config cycles). 

We need to rethink the PCI config stuff per Stepan's comment, in part 
because the device tree now includes things that are NOT PCI devices. 
Stepan's suggestion, to make the functions take busdevfn as the 
parameter, makes a lot of sense. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.s


git-svn-id: svn://coreboot.org/repository/coreboot-v3@720 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-05 01:19:37 +00:00
Ronald G. Minnich
84c313733d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@718 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-03 23:36:44 +00:00
Ronald G. Minnich
30c0db46ed We're getting closer. It has been pointed out that this code is not pretty. I agree. Get
it working, then we'll get it pretty. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@717 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-03 22:42:01 +00:00
Peter Stuge
41242a63c3 v3: k8/m57sli wip1
This is not nearly complete, but just the current state of my tree.

k8/raminit.c does not compile at all. Lots of fixes are still needed to bring
it working into v3. I've gone through about 1/8 of the file, it errors out on
line 576 now.

The mcp55 files are in a very early state and also do not compile for me, so
I've disabled them by commenting out the select in mainboard/gigabyte/Kconfig.

Once northbridge/amd/k8/raminit.c builds, k8_ops needs to be added, then we
may actually see the first v3 k8 build. :)

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@713 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-02 03:34:05 +00:00
Ronald G. Minnich
526a61a6e5 rename per IRC
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@706 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 18:00:54 +00:00
Ronald G. Minnich
06ced7c09a The m57sli almost builds. It's pretty empty. The dtc is not run .
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@702 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 17:03:22 +00:00
Ronald G. Minnich
96914e1655 1. geodelx.c: cover case of unterminated DRAM by adding a terminated
parameter to two functions. 
2. geodelx.h: define DRAM_TERMINATED and DRAM_UNTERMINATED constants
3. dbe62/initram.c: move to auto PLL control, so set MANUALCONF to 0
4. all other initram.c: set up calls to cpu_reg_init with proper 
   TERMINATED/UNTERMINATED constants. 

builds for dbe62. The auto PLL strapping is tested and works. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@699 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-29 15:54:46 +00:00
Ronald G. Minnich
bc75f3349d Add names for control bits.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>



Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@698 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-25 19:44:08 +00:00
Ronald G. Minnich
14c3feacff This adds support for AMD graphics initialization.
Note: You MUST have the later AMD VSA code that does not call bios 
interrupts. If you use the older code, your boot will hang at this 
point:
buf[0x20] signature is b0:10:e6:80
Call real_mode_switch_call_vsm

With post code 10

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@616 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-22 01:58:09 +00:00
Carl-Daniel Hailfinger
31a9e22fa4 A lot of the v3 header files require other header files to be #included
before they can be #included. That is completely counter-intuitive. Add 
necessary #includes to the header files themselves.

Fix a few cases where nonexisting files were #included.

Compile tested on Qemu and Alix1C.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@611 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-19 00:34:32 +00:00
Carl-Daniel Hailfinger
7980349f4f Remove dead code protected by #if 0 since it appeared.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com> 


git-svn-id: svn://coreboot.org/repository/coreboot-v3@602 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-15 23:58:09 +00:00
Carl-Daniel Hailfinger
5d11489d74 Make printk() log to a buffer.
Tested on Qemu and Geode LX.
Benefits of this patch:
- printk() now works directly after printk_buffer_init(), even before
the serial port is set up.
- If all you want is a log, you don't have to bother with serial output.
- A payload can read and analyze the log.
- You can build on this and buffer log until serial is available, then
flush the messages buffered so far.

The printk buffer is configurable with a default-on Kconfig variable.

If you want to dump the buffer from the Qemu monitor after CAR has been
disabled, use this command:
memsave 0x90000 65536 memdump.bin

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@590 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-13 15:48:37 +00:00
Carl-Daniel Hailfinger
e1cbfaac02 CAR size and CAR base defines are scattered all over the place. Set them
centrally from Kconfig, but keep the Kconfig variables hidden.
That way, they are available everywhere, you don't have to try to guess
where they are set, and they come with help text if you look at
arch/x86/Kconfig.
No semantic changes, although some of the settings really could use an
overhaul.

This also is a requirement for my printk buffer patch.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@587 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-11 01:30:24 +00:00
Ronald G. Minnich
0044d53a10 This set of changes creates irq tables for alix1c and adds the functions
from v2 to install them. Linux boots fine and all interrupts
seem to work correctly -- the network comes up, USB hot plug works, 
I can mount the USB disk, etc. 

To enable pirq tables for a given mainboard, simply add the 
select PIRQ_TABLE (see below) to the Kconfig for that board. 

Again, this code builds and boots linux on the alix1c.

I think, with this change, we are very close to moving ALL LX boards to 
v3 and deprecating v2. The major remaining fix is to add an empty LAR 
entry to fill empty space in LAR and speed up the LAR file search 
process. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Index: include/tables.h
Add prototype, conditioned on CONFIG_PIRQ_TABLE

Index: util/x86emu/vm86.c
Comment out 'debug trap' code that scribbles vectors at 0x4000. 
I don't know why this is here, but I'd like to leave it #if'ed out --
somebody, at some point, thought we needed it. To reenable, we will need
to move stage2 code or these magic vectors. 

Index: arch/x86/Makefile
Add support for conditional compilation of pirq support code. 

Index: arch/x86/pirq_routing.c
Add this file from v2. 

Index: arch/x86/archtables.c
Add call to write_pirq_routing_table (controlled by #ifdef
CONFIG_PIRQ_TABLE)

Index: arch/x86/Kconfig
Add new config variable: PIRQ_TABLE

Index: device/device.c
Fix some trivial bugs. 

Index: mainboard/pcengines/alix1c/Makefile
Add pirq table code for stage2

Index: mainboard/pcengines/alix1c/dts
Modify dts to properly set southbridge variables

Index: mainboard/pcengines/alix1c/irq_tables.c
Add code from v2 for the alix1c. 

Index: mainboard/pcengines/Kconfig
Add 'select PIRQ_TABLE'

Index: include/arch/x86/pirq_routing.h
Add include file from v2.
Remove all the SLOTCOUNT nonsense. This hack was only needed
for a very early version of gcc 3.x, where they screwed up the 
creation of struct members that used the [] syntax for variable-length
array at the end of the struct. 

Index: include/device/pci.h
Add prototype



git-svn-id: svn://coreboot.org/repository/coreboot-v3@582 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-09 16:32:59 +00:00
Marc Jones
5917206641 Cache the ROM to speed up stage2 and payload decompression.
Due to some problems with PCI transactions, Geode LX needs the ROM cache properties to be write-serialize + cache disabled by runtime. More details below.

Add mainboard_pre_payload() call to each mainboard as the final coreboot function before the payload is called by stage1.

Note that this patch also grows the bootblock from 16K to 20K to make room for mainboard_pre_payload().

"The problem is a transaction depth issue and bottlenecks inside the GX
and LX that go across PCI.  The conditions are very complicated but it
comes down to we need write serialization for writes to PCI. If you
look in the data book you can't have write serialization and the cache
enabled on a given area. During coreboot we don't have to worry about
a write or a PCI bus master so I think we can enable caching the ROM.
After coreboot we can't be sure what will happen in the system so we
need to set it up to be safe. For example flashrom just clears the
write protect bit. If the cache were enabled (no write serialization)
and flashrom was writing the ROM we would be in a precarious position.
A PCI  bus master doing a read or a write that has a hit on a tag
would cause enough bottleneck conditions that it might hit the bug. We
could change flashrom but that doesn't help other tools. We need to
leave the system in a safe state. Also, caching the ROM after it is no
longer used doesn't make much sense. So, we need a call just before
the payload runs to clean up the system."

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@573 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-06 02:36:50 +00:00
Stefan Reinauer
6220b632e7 Now version 3: LinuxBIOS -> coreboot rename.
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-27 18:54:57 +00:00
Carl-Daniel Hailfinger
75c6c210de include/arch/x86/amd_geodelx.h had duplicated #defines by accident in
r546. Remove them again.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@547 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-05 01:33:28 +00:00
Carl-Daniel Hailfinger
888063b4af These changes implement a fixed Geode LX Cache As Ram that allows a
return from disable_car.
- Move the cache as ram memory to 0x80000 instead of 0xc8000, as the C
  range is really tricky to get right :-)
- Modify the geode disable_car to ensure the cache is flushed to ram on
  the wbinvd.

With these changes, I get a payload loaded.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@546 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-04 23:19:49 +00:00
Carl-Daniel Hailfinger
cbbddbe4db Move AMD Geode LX defines for CAR from a .S to a .h so they are
available to C.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@543 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-04 12:53:09 +00:00
Uwe Hermann
497cdb7484 Constify structs which can be const.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@519 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-11-26 13:28:52 +00:00
Uwe Hermann
441145f9fe Add comment, small style fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@514 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-11-21 18:25:20 +00:00
Uwe Hermann
7467eba22a Various code cleanups:
- Simplify lots of code, especially msr-related code.

 - Move struct msrinit declaration into msr.h as we use it quite often
   and there's no use to duplicate it again and again in each file.

 - Remove unrequired variable usage (e.g. numEnabled, msrnum, val, port).

 - Remove useless comments.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@464 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-23 23:18:41 +00:00
Uwe Hermann
7705f6a682 Various smaller code fixes:
- Use 'static' for functions and structs which are not meant to be public.

 - Use 'const' for variables which are not meant to be modified.

 - Move some prototypes into legacy.h where they belong.

 - Drop prototypes for non-existing functions.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@460 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-20 14:03:39 +00:00
Uwe Hermann
50cdf3827d Merge hlt() into cpu.h where it belongs. Add some documentation.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@449 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-12 13:01:42 +00:00
Uwe Hermann
6d2a927124 Remove some include files which are not required (and add some which are).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@448 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-12 01:26:43 +00:00
Marc Jones
22895ba000 Rework the Geode delay control setup to table driven and much more readable.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@435 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-06 18:03:43 +00:00
Marc Jones
7c9c8db800 Moved some generic 8254 PIT #defines out of the speaker code to legacy.h.
Use legacy.h PIT defines in Geode code.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@433 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-05 16:58:10 +00:00
Marc Jones
b1ef1489a0 Clean up comments and #defines in Geode LX code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@432 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-03 20:33:33 +00:00
Uwe Hermann
4fff36c35c Document origin of include/arch/x86/arch/spinlock.h and use proper
header. Some other minor fixes (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@431 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-03 16:58:16 +00:00
Stefan Reinauer
eec93e2ecb * fix copyright headers to v2 only as suggested by Uwe
* drop silly code when not using SMP
* fix device/device.c
* drop spinlock_t, use struct spinlock instead.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

one kitten died already! ;-)



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@429 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-30 22:55:10 +00:00
Uwe Hermann
b636ab9cf1 Bring the file cpu.h in sync with the current version of the code in
the Linux kernel (as far as possible). The code is a lot simpler
and shorter now.

Also, add cpu_relax() (which is also part of the Linux file) which
could be useful for busy-loops (but is currently not used).
Drop the cpu_relax() from spinlock.h as it's not spinlock related in any way.

The code builds, and works in QEMU, but is not tested on hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@423 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-30 16:57:33 +00:00
Stefan Reinauer
25ebd9110b * start using arch/foo.h again instead of archfoo.h (trivial)
* make constructor an initializer.
* fix memory leak/code flow error in current code
* add spinlocking
* drop malloc and use new_device for device allocation instead.
* add CONFIG_SMP as it is needed by spinlocks and soon other stuff.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@418 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-29 16:57:23 +00:00
Ronald G. Minnich
782329e647 two more unsigned!
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@409 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-29 00:23:18 +00:00
Ronald G. Minnich
db20555a2c minor cleanup; trivial fix so I'm just committing it.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@408 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-29 00:22:19 +00:00
Ronald G. Minnich
7044158043 remmove mst_t from include and southbridge.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@396 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-28 17:00:36 +00:00
Ronald G. Minnich
bb554c234a Change case and improve comments.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@393 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-28 15:19:30 +00:00
Uwe Hermann
2a605775a6 Various cosmetic license header fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@392 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-28 14:06:39 +00:00
Ronald G. Minnich
1e3cd03815 Add a few functions.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@378 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-27 20:01:10 +00:00
Ronald G. Minnich
8fbafe7ed4 AMD geode defines.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@377 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-27 19:57:48 +00:00
Uwe Hermann
f1f8bc2cd4 Document the origins of include/arch/x86/cpu.h (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@367 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-26 13:46:57 +00:00
Ronald G. Minnich
33c16b873a This adds cpu info support for v3. Other arch-specific cpu support
should go here. This file taken from V2.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@365 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-25 21:15:44 +00:00
Ronald G. Minnich
db83d17b19 add msr.h to v3
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@335 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-05-24 20:33:46 +00:00
Uwe Hermann
464ef4613d Use the same naming convention and placement for "include guards" in
all header files.

This closes #40, as I think we don't need to invest time to fix this in
LinuxBIOSv2, but only in LinuxBIOSv3.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@332 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-05-21 06:48:47 +00:00