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Add names for control bits.

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Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>



Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@698 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-07-25 19:44:08 +00:00
parent b1596f216b
commit bc75f3349d
1 changed files with 15 additions and 0 deletions
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15
include/arch/x86/amd_geodelx.h
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@ -230,6 +230,21 @@
#define DM_CONFIG0_LOWER_DCDIS_SET (1 << 8)
#define DM_CONFIG0_LOWER_MISSER_SET (1<<1)
/* Region CONFiguration registers (RCONF) */
/* There are control bits for memory configuration. They are at different
* offsets depending on the MSR. We define them here with values
* independent of their position in a 64-bit MSR, with a "shift" value
* to get them into the right place. To use them for, e.g., the
* CPU_RCONF_DEFAULT register, you would use
* RCONF_WT(RCONF_DEFAULT_LOWER_SYSRC_SHIFT)
*/
#define RCONF_WS(x) (1<<(5+x)) /* Write-serialize */
#define RCONF_WC(x) (1<<(4+x)) /* Write-combine */
#define RCONF_WT(x) (1<<(3+x)) /* Write-through */
#define RCONF_WP(x) (1<<(2+x)) /* Write-protect */
#define RCONF_WA(x) (1<<(1+x)) /* Write-allocate */
#define RCONF_CD(x) (1<<(0+x)) /* Cache Disable */
#define CPU_RCONF_DEFAULT 0x1808
#define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24
#define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4