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https://github.com/fail0verflow/switch-coreboot.git
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Add lapic defines and support.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@745 f3766cd6-281f-0410-b1cd-43a5c92072e9
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Ronald G. Minnich
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2 changed files with 279 additions and 0 deletions
168
include/arch/x86/lapic.h
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168
include/arch/x86/lapic.h
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/*
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* This file is part of the coreboot project.
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* Copyright (C) 2004 Linux Networx
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* (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
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* Copyright (C) 2005 Stefan Reinauer <stepan@coresystems.de>
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* Copyright (C) 2007 AMD Marc Jones
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef CPU_X86_LAPIC_H
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#define CPU_X86_LAPIC_H
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#include <cpu.h>
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#include <lapic_def.h>
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#include <msr.h>
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/* See if I need to initialize the local apic */
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#if defined(CONFIG_SMP) || defined(CONFIG_IOAPIC)
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# define NEED_LAPIC 1
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#endif
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static inline __attribute__((always_inline)) unsigned long lapic_read(unsigned long reg)
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{
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return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg));
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}
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static inline __attribute__((always_inline)) void lapic_write(unsigned long reg, unsigned long v)
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{
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*((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v;
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}
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static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
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{
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do { } while ( lapic_read( LAPIC_ICR ) & LAPIC_ICR_BUSY );
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}
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static inline void enable_lapic(void)
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{
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struct msr msr;
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msr = rdmsr(LAPIC_BASE_MSR);
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msr.hi &= 0xffffff00;
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msr.lo &= 0x000007ff;
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msr.lo |= LAPIC_DEFAULT_BASE | (1 << 11);
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wrmsr(LAPIC_BASE_MSR, msr);
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}
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static inline void disable_lapic(void)
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{
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struct msr msr;
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msr = rdmsr(LAPIC_BASE_MSR);
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msr.lo &= ~(1 << 11);
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wrmsr(LAPIC_BASE_MSR, msr);
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}
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static inline __attribute__((always_inline)) unsigned long lapicid(void)
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{
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return lapic_read(LAPIC_ID) >> 24;
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}
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static inline __attribute__((always_inline)) void stop_this_cpu(void)
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{
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/* Called by an AP when it is ready to halt and wait for a new task */
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for(;;) {
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hlt();
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}
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}
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#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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/*
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* but generally the primitive is invalid, *ptr is output argument. --ANK
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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:"=q" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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}
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return x;
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}
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extern inline void lapic_write_atomic(unsigned long reg, unsigned long v)
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{
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xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v);
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}
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#ifdef CONFIG_X86_GOOD_APIC
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# define FORCE_READ_AROUND_WRITE 0
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# define lapic_read_around(x) lapic_read(x)
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# define lapic_write_around(x,y) lapic_write((x),(y))
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#else
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# define FORCE_READ_AROUND_WRITE 1
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# define lapic_read_around(x) lapic_read(x)
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# define lapic_write_around(x,y) lapic_write_atomic((x),(y))
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#endif
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static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
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{
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int timeout;
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unsigned long status;
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int result;
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lapic_wait_icr_idle();
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lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
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lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
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timeout = 0;
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do {
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#if 0
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udelay(100);
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#endif
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status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
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} while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
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result = -1;
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if (status == LAPIC_ICR_RR_VALID) {
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*pvalue = lapic_read(LAPIC_RRR);
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result = 0;
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}
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return result;
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}
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void setup_lapic(void);
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#ifdef CONFIG_SMP
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struct device;
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int start_cpu(struct device *cpu);
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#endif /* CONFIG_SMP */
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#endif /* CPU_X86_LAPIC_H */
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111
include/arch/x86/lapic_def.h
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111
include/arch/x86/lapic_def.h
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@ -0,0 +1,111 @@
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/*
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* This file is part of the coreboot project.
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* Copyright (C) 2004 Linux Networx
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* (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
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* Copyright (C) 2005 Stefan Reinauer <stepan@coresystems.de>
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* Copyright (C) 2007 AMD Marc Jones
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef CPU_X86_LAPIC_DEF_H
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#define CPU_X86_LAPIC_DEF_H
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#define LAPIC_BASE_MSR 0x1B
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#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8)
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#define LAPIC_BASE_MSR_ENABLE (1 << 11)
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#define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000
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#define LAPIC_DEFAULT_BASE 0xfee00000
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#define LAPIC_ID 0x020
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#define LAPIC_LVR 0x030
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#define LAPIC_TASKPRI 0x80
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#define LAPIC_TPRI_MASK 0xFF
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#define LAPIC_ARBID 0x090
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#define LAPIC_RRR 0x0C0
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#define LAPIC_SVR 0x0f0
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#define LAPIC_SPIV 0x0f0
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#define LAPIC_SPIV_ENABLE 0x100
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#define LAPIC_ESR 0x280
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#define LAPIC_ESR_SEND_CS 0x00001
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#define LAPIC_ESR_RECV_CS 0x00002
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#define LAPIC_ESR_SEND_ACC 0x00004
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#define LAPIC_ESR_RECV_ACC 0x00008
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#define LAPIC_ESR_SENDILL 0x00020
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#define LAPIC_ESR_RECVILL 0x00040
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#define LAPIC_ESR_ILLREGA 0x00080
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#define LAPIC_ICR 0x300
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#define LAPIC_DEST_SELF 0x40000
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#define LAPIC_DEST_ALLINC 0x80000
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#define LAPIC_DEST_ALLBUT 0xC0000
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#define LAPIC_ICR_RR_MASK 0x30000
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#define LAPIC_ICR_RR_INVALID 0x00000
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#define LAPIC_ICR_RR_INPROG 0x10000
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#define LAPIC_ICR_RR_VALID 0x20000
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#define LAPIC_INT_LEVELTRIG 0x08000
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#define LAPIC_INT_ASSERT 0x04000
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#define LAPIC_ICR_BUSY 0x01000
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#define LAPIC_DEST_LOGICAL 0x00800
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#define LAPIC_DM_FIXED 0x00000
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#define LAPIC_DM_LOWEST 0x00100
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#define LAPIC_DM_SMI 0x00200
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#define LAPIC_DM_REMRD 0x00300
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#define LAPIC_DM_NMI 0x00400
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#define LAPIC_DM_INIT 0x00500
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#define LAPIC_DM_STARTUP 0x00600
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#define LAPIC_DM_EXTINT 0x00700
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#define LAPIC_VECTOR_MASK 0x000FF
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#define LAPIC_ICR2 0x310
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#define GET_LAPIC_DEST_FIELD(x) (((x)>>24)&0xFF)
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#define SET_LAPIC_DEST_FIELD(x) ((x)<<24)
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#define LAPIC_LVTT 0x320
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#define LAPIC_LVTPC 0x340
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#define LAPIC_LVT0 0x350
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#define LAPIC_LVT_TIMER_BASE_MASK (0x3<<18)
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#define GET_LAPIC_TIMER_BASE(x) (((x)>>18)&0x3)
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#define SET_LAPIC_TIMER_BASE(x) (((x)<<18))
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#define LAPIC_TIMER_BASE_CLKIN 0x0
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#define LAPIC_TIMER_BASE_TMBASE 0x1
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#define LAPIC_TIMER_BASE_DIV 0x2
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#define LAPIC_LVT_TIMER_PERIODIC (1<<17)
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#define LAPIC_LVT_MASKED (1<<16)
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#define LAPIC_LVT_LEVEL_TRIGGER (1<<15)
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#define LAPIC_LVT_REMOTE_IRR (1<<14)
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#define LAPIC_INPUT_POLARITY (1<<13)
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#define LAPIC_SEND_PENDING (1<<12)
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#define LAPIC_LVT_RESERVED_1 (1<<11)
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#define LAPIC_DELIVERY_MODE_MASK (7<<8)
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#define LAPIC_DELIVERY_MODE_FIXED (0<<8)
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#define LAPIC_DELIVERY_MODE_NMI (4<<8)
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#define LAPIC_DELIVERY_MODE_EXTINT (7<<8)
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#define GET_LAPIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
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#define SET_LAPIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
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#define LAPIC_MODE_FIXED 0x0
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#define LAPIC_MODE_NMI 0x4
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#define LAPIC_MODE_EXINT 0x7
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#define LAPIC_LVT1 0x360
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#define LAPIC_LVTERR 0x370
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#define LAPIC_TMICT 0x380
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#define LAPIC_TMCCT 0x390
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#define LAPIC_TDCR 0x3E0
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#define LAPIC_TDR_DIV_TMBASE (1<<2)
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#define LAPIC_TDR_DIV_1 0xB
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#define LAPIC_TDR_DIV_2 0x0
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#define LAPIC_TDR_DIV_4 0x1
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#define LAPIC_TDR_DIV_8 0x2
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#define LAPIC_TDR_DIV_16 0x3
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#define LAPIC_TDR_DIV_32 0x8
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#define LAPIC_TDR_DIV_64 0x9
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#define LAPIC_TDR_DIV_128 0xA
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#endif /* CPU_X86_LAPIC_DEF_H */
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