We're getting closer. It has been pointed out that this code is not pretty. I agree. Get

it working, then we'll get it pretty. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@717 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-08-03 22:42:01 +00:00
parent c945259136
commit 30c0db46ed
10 changed files with 192 additions and 79 deletions

View file

@ -42,6 +42,13 @@ $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c: $(obj)/util/options/build_opt_t
--config $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout \
--option $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
$(obj)/mainboard/$(MAINBOARDDIR)/option_table.h: $(obj)/util/options/build_opt_tbl $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout
$(Q)printf " OPTIONS $(subst $(shell pwd)/,,$(@))\n"
$(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)
$(Q)$(obj)/util/options/build_opt_tbl -b \
--config $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout \
--header $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
$(obj)/option_table: $(obj)/mainboard/$(MAINBOARDDIR)/option_table.o
$(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(OBJCOPY) -O binary $< $@

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@ -22,6 +22,7 @@
#include <lib.h>
#include <console.h>
#include <msr.h>
#include <macros.h>
#include <amd/k8/k8.h>
/**

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@ -17,11 +17,11 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "../macros.h"
#define ASSEMBLY
#include <macros.h>
#define CacheSize CONFIG_CARSIZE
#define CacheBase CONFIG_CARBASE
#define MEM_TOPK 2048
#define ASSEMBLY
/* leave some space for global variable to pass to RAM stage */
#define GlobalVarSize 32

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@ -1,29 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000 Ron G. Minnich <rminnich@lanl.gov>
* Copyright (C) 2007 Stefan Reinauer <stepan@coresystems.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef ARCH_X86_MACROS_H
#define ARCH_X86_MACROS_H
#define port80_post(value) \
movb $value, %al; \
outb %al, $0x80
#endif /* ARCH_X86_MACROS_H */

View file

@ -322,4 +322,14 @@ int check_normal_boot_flag(void)
return (byte & RTC_NORMAL_BOOT_FLAG_SET);
}
unsigned read_option(unsigned start, unsigned size, unsigned def)
{
#ifdef CONFIG_OPTION_TABLE
unsigned byte;
byte = CMOS_READ(start/8);
return (byte >> (start & 7U)) & ((1U << size) - 1U);
#else
return def;
#endif
}

View file

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2006-2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -282,3 +282,124 @@
#define NBCAP_MEMCLK_166MHZ 1
#define NBCAP_MEMCLK_200MHZ 0
#define NBCAP_MEMCTRL (1 << 8)
/* resources for the routing in the northbridge. These may be family specific;
* the were in v2.
*/
#define RES_DEBUG 0
#define RES_PCI_IO 0x10
#define RES_PORT_IO_8 0x22
#define RES_PORT_IO_32 0x20
#define RES_MEM_IO 0x40
#ifndef ASSEMBLY
/* cpu version -- no support for f0 yet */
static inline int is_cpu_rev_a0(void)
{
return (cpuid_eax(1) & 0xfffef) == 0x0f00;
}
static inline int is_cpu_pre_c0(void)
{
return (cpuid_eax(1) & 0xfffef) < 0x0f48;
}
static inline int is_cpu_c0(void)
{
return (cpuid_eax(1) & 0xfffef) == 0x0f48;
}
static inline int is_cpu_pre_b3(void)
{
return (cpuid_eax(1) & 0xfffef) < 0x0f41;
}
static inline int is_cpu_b3(void)
{
return (cpuid_eax(1) & 0xfffef) == 0x0f41;
}
//AMD_D0_SUPPORT
static inline int is_cpu_pre_d0(void)
{
return (cpuid_eax(1) & 0xfff0f) < 0x10f00;
}
static inline int is_cpu_d0(void)
{
return (cpuid_eax(1) & 0xfff0f) == 0x10f00;
}
//AMD_E0_SUPPORT
static inline int is_cpu_pre_e0(void)
{
return (cpuid_eax(1) & 0xfff0f) < 0x20f00;
}
static inline int is_cpu_e0(void)
{
return (cpuid_eax(1) & 0xfff00) == 0x20f00;
}
/* note: we'd like to have this sysinfo common to all K8, there's no need to
* have one different kind per different kind of k8 at this point.
*/
//#include "raminit.h"
struct dimm_size {
u8 per_rank; // it is rows + col + bank_lines + data lines */
u8 rows;
u8 col;
u8 bank; //1, 2, 3 mean 2, 4, 8
u8 rank;
} __attribute__((packed));
struct mem_info { // pernode
u32 dimm_mask;
struct dimm_size sz[DIMM_SOCKETS];
u32 x4_mask;
u32 x16_mask;
u32 single_rank_mask;
u32 page_1k_mask;
// u32 ecc_mask;
// u32 registered_mask;
u8 is_opteron;
u8 is_registered;
u8 is_ecc;
u8 is_Width128;
u8 memclk_set; // we need to use this to retrieve the mem param
u8 rsv[3];
} __attribute__((packed));
struct link_pair_st {
struct device * udev;
u32 upos;
u32 uoffs;
struct device * dev;
u32 pos;
u32 offs;
} __attribute__((packed));
struct sys_info {
u8 ctrl_present[NODE_NUMS];
struct mem_info meminfo[NODE_NUMS];
struct mem_controller ctrl[NODE_NUMS];
u8 mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail
u32 tom_k;
u32 tom2_k;
u32 mem_base[NODE_NUMS];
u32 cs_base[NODE_NUMS*8]; //8 cs_idx
u32 hole_reg[NODE_NUMS]; // can we spare it to one, and put ctrl idx in it
u8 dqs_delay_a[NODE_NUMS*2*2*9]; //8 node channel 2, direction 2 , bytelane *9
u8 dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8
u32 nodes;
struct link_pair_st link_pair[16];// enough? only in_conherent
u32 link_pair_num;
u32 ht_c_num;
u32 sbdn;
u32 sblk;
u32 sbbusn;
} __attribute__((packed));
#endif /* ! ASSEMBLY */

View file

@ -22,7 +22,7 @@
#define HC_POSSIBLE_NUM 8
struct amdk8_sysconf_t {
struct amdk8_sysconf{
//ht
unsigned nodes;
unsigned hc_possible_num;

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@ -155,33 +155,32 @@
#define PCI_VENDOR_ID_CIRRUS 0x1013
#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 /* Used by QEMU */
#define PCI_VENDIR_ID_NVIDIA 0x10de
/*
0360MCP55 LPC Bridge
0361MCP55 LPC Bridge
0362MCP55 LPC Bridge
0363MCP55 LPC Bridge
0364MCP55 LPC Bridge
0365MCP55 LPC Bridge
0366MCP55 LPC Bridge
0367MCP55 LPC Bridge
0368MCP55 SMBus
0369MCP55 Memory Controller
036aMCP55 Memory Controller
036bMCP55 SMU
036cMCP55 USB Controller
036dMCP55 USB Controller
036eMCP55 IDE
0370MCP55 PCI bridge
0371MCP55 High Definition Audio
0372MCP55 Ethernet
0373MCP55 Ethernet
0374MCP55 PCI Express bridge
0375MCP55 PCI Express bridge
0376MCP55 PCI Express bridge
0377MCP55 PCI Express bridge
0378MCP55 PCI Express bridge
037aMCP55 Memory Controller
*/
#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIBRIDGE 0x370
#define PCI_VENDOR_ID_NVIDIA 0x10de
#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC 0x0360
#define PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE 0x0361
#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2 0x0362
#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3 0x0363
#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4 0x0364
#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5 0x0365
#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6 0x0366
#define PCI_DEVICE_ID_NVIDIA_MCP55_PRO 0x0367
#define PCI_DEVICE_ID_NVIDIA_MCP55_SM2 0x0368
#define PCI_DEVICE_ID_NVIDIA_MCP55_IDE 0x036E
#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA0 0x037E
#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA1 0x037F
#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC 0x0372
#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE 0x0373
#define PCI_DEVICE_ID_NVIDIA_MCP55_AZA 0x0371
#define PCI_DEVICE_ID_NVIDIA_MCP55_USB 0x036C
#define PCI_DEVICE_ID_NVIDIA_MCP55_USB2 0x036D
#define PCI_DEVICE_ID_NVIDIA_MCP55_PCI 0x0370
#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C 0x0374
#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E 0x0375
#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A 0x0376
#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F 0x0377
#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D 0x0378
#define PCI_DEVICE_ID_NVIDIA_MCP55_HT 0x0369
#define PCI_DEVICE_ID_NVIDIA_MCP55_TRIM 0x036A
#define PCI_DEVICE_ID_NVIDIA_MCP55_PMU 0x036B
#endif /* DEVICE_PCI_IDS_H */

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@ -19,7 +19,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \
$(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c

View file

@ -32,15 +32,25 @@
#include <console.h>
#include <mtrr.h>
#include <macros.h>
#include <spd.h>
#include <cpu.h>
#include <msr.h>
#include <amd/k8/raminit.h>
#include <amd/k8/k8.h>
#include <amd/k8/sysconf.h>
#include <device/pci.h>
#include <mc146818rtc.h>
#include <lib.h>
#ifndef QRANK_DIMM_SUPPORT
#define QRANK_DIMM_SUPPORT 0
#endif
#ifndef HW_MEM_HOLE_SIZEK
#define HW_MEM_HOLE_SIZEK 64*1024*1024
#endif
static void hard_reset(void);
static void setup_resource_map(const unsigned int *register_values, int max)
@ -566,14 +576,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
static void hw_enable_ecc(const struct mem_controller *ctrl)
{
u32 dcl, nbcap;
u32 dcl, nbcap, opt = 1;
nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~DCL_DimmEccEn;
if (nbcap & NBCAP_ECC) {
dcl |= DCL_DimmEccEn;
}
if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
if (get_option(&opt, "ECC_memory") || opt) {
dcl &= ~DCL_DimmEccEn;
}
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
@ -610,16 +620,6 @@ static int is_registered(const struct mem_controller *ctrl)
return !(dcl & DCL_UnBufDimm);
}
struct dimm_size {
unsigned long side1;
unsigned long side2;
unsigned long rows;
unsigned long col;
#if QRANK_DIMM_SUPPORT == 1
unsigned long rank;
#endif
};
static struct dimm_size spd_get_dimm_size(unsigned device)
{
/* Calculate the log base 2 size of a DIMM in bits */
@ -1118,8 +1118,9 @@ unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
static void order_dimms(const struct mem_controller *ctrl)
{
unsigned long tom_k, base_k;
int opt = 1;
if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
if (get_option(&opt, "interleave_chip_selects") || opt) {
tom_k = interleave_chip_selects(ctrl);
} else {
printk(BIOS_DEBUG, "Interleaving disabled\n");
@ -1405,6 +1406,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
unsigned min_cycle_time, min_latency, bios_cycle_time;
int i;
u32 value;
u32 max_mem_clk_index = 0;
static const u8 latency_indicies[] = { 26, 23, 9 };
static const unsigned char min_cycle_times[] = {
@ -1417,8 +1419,9 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
bios_cycle_time = min_cycle_times[
read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
get_option(&max_mem_clk_index, "max_mem_clk");
bios_cycle_time = min_cycle_times[max_mem_clk_index];
if (bios_cycle_time > min_cycle_time) {
min_cycle_time = bios_cycle_time;
}
@ -2111,7 +2114,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sy
return;
hw_spd_err:
/* Unrecoverable error reading SPD data */
print_err("SPD error - reset\n");
printk(BIOS_ERR, "SPD error - reset\n");
hard_reset();
return;
}