mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
This adds support for AMD graphics initialization.
Note: You MUST have the later AMD VSA code that does not call bios interrupts. If you use the older code, your boot will hang at this point: buf[0x20] signature is b0:10:e6:80 Call real_mode_switch_call_vsm With post code 10 Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@616 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
parent
897ea2e08b
commit
14c3feacff
8 changed files with 195 additions and 100 deletions
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@ -1254,7 +1254,7 @@ static inline void vr_write(u16 class_index, u16 data)
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* @param class_index The register index
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* @return the 16-bit word of data
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*/
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static inline u16 vr_ead(u16 class_index)
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static inline u16 vr_read(u16 class_index)
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{
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u16 data;
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outl(((u32) VR_UNLOCK << 16) | class_index, VRC_INDEX);
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@ -29,6 +29,8 @@
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/config/("northbridge/amd/geodelx/domain");
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pci@1,0 {
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/config/("northbridge/amd/geodelx/pci");
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/* Video RAM has to be in 2MB chunks. */
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geode_video_mb = "8";
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};
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pci@15,0 {
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/config/("southbridge/amd/cs5536/dts");
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@ -23,6 +23,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y)
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STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \
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$(obj)/northbridge/amd/geodelx/vsmsetup.o \
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$(obj)/util/x86emu/vm86_gdt.o
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$(obj)/util/x86emu/vm86_gdt.o \
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$(obj)/northbridge/amd/geodelx/grphinit.o
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endif
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78
northbridge/amd/geodelx/geodelink.h
Normal file
78
northbridge/amd/geodelx/geodelink.h
Normal file
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@ -0,0 +1,78 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef GEODELINK_H
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#define GEODELINK_H
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struct gliutable {
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unsigned long desc_name;
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unsigned short desc_type;
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unsigned long hi, lo;
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};
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static const struct gliutable gliu0table[] = {
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/* 0-7FFFF to MC */
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{.desc_name = MSR_GLIU0_BASE1,.desc_type = BM,.hi = MSR_MC + 0x0,
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.lo = 0x0FFF80},
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/* 80000-9FFFF to MC */
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{.desc_name = MSR_GLIU0_BASE2,.desc_type = BM,.hi = MSR_MC + 0x0,
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.lo = (0x80 << 20) + 0x0FFFE0},
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/* C0000-FFFFF split to MC and PCI (sub decode) A0000-BFFFF
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* handled by SoftVideo.
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*/
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{.desc_name = MSR_GLIU0_SHADOW,.desc_type = SC_SHADOW,
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.hi = MSR_MC + 0x0,.lo = 0x03},
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/* Catch and fix dynamically. */
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{.desc_name = MSR_GLIU0_SYSMEM,.desc_type = R_SYSMEM,
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.hi = MSR_MC,.lo = 0x0},
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/* Catch and fix dynamically. */
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{.desc_name = MSR_GLIU0_SMM,.desc_type = BMO_SMM,
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.hi = MSR_MC,.lo = 0x0},
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{.desc_name = GLIU0_GLD_MSR_COH,.desc_type = OTHER,
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.hi = 0x0,.lo = GL0_CPU},
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{.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},
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};
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static const struct gliutable gliu1table[] = {
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/* 0-7FFFF to MC */
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{.desc_name = MSR_GLIU1_BASE1,.desc_type = BM,.hi = MSR_GL0 + 0x0,
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.lo = 0x0FFF80},
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/* 80000-9FFFF to MC */
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{.desc_name = MSR_GLIU1_BASE2,.desc_type = BM,.hi = MSR_GL0 + 0x0,
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.lo = (0x80 << 20) + 0x0FFFE0},
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/* C0000-Fffff split to MC and PCI (sub decode) */
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{.desc_name = MSR_GLIU1_SHADOW,.desc_type = SC_SHADOW,
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.hi = MSR_GL0 + 0x0,.lo = 0x03},
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/* Catch and fix dynamically. */
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{.desc_name = MSR_GLIU1_SYSMEM,.desc_type = R_SYSMEM,
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.hi = MSR_GL0,.lo = 0x0},
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/* Catch and fix dynamically. */
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{.desc_name = MSR_GLIU1_SMM,.desc_type = BM_SMM,
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.hi = MSR_GL0,.lo = 0x0},
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{.desc_name = GLIU1_GLD_MSR_COH,.desc_type = OTHER,
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.hi = 0x0,.lo = GL1_GLIU0},
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/* FooGlue FPU 0xF0 */
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{.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type = SCIO,
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.hi = (GL1_GLCP << 29) + 0x0,.lo = 0x033000F0},
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{.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},
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};
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static struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
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#endif /* GEODELINK_H */
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -25,12 +25,14 @@
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#include <device/pci_ids.h>
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#include <msr.h>
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#include <amd_geodelx.h>
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#include <statictree.h>
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#include "geodelink.h"
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/* Function prototypes */
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extern void chipsetinit(void);
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extern u32 get_systop(void);
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extern void northbridge_init_early(void);
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extern void graphics_init(struct northbridge_amd_geodelx_pci_config *nb_pci);
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extern u64 sizeram(void);
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/**
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* Currently not set up.
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@ -41,6 +43,37 @@ static void enable_shadow(struct device *dev)
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{
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}
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/**
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* TODO.
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*
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* @return TODO.
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*/
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u64 get_systop(struct northbridge_amd_geodelx_pci_config *nb_pci)
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{
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struct gliutable *gl = NULL;
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u64 systop;
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struct msr msr;
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int i;
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for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
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if (gliu0table[i].desc_type == R_SYSMEM) {
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gl = &gliu0table[i];
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break;
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}
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}
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if (gl) {
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msr = rdmsr(gl->desc_name);
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systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8);
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systop += 4 * 1024; /* 4K */
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} else {
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systop =
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(((sizeram() - nb_pci->geode_video_mb) * 1024) - SMM_SIZE) * 1024;
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}
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return systop;
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}
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/**
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* Initialize the northbridge PCI device.
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* Right now this a no op. We leave it here as a hook for later use.
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@ -116,6 +149,8 @@ static void geodelx_pci_domain_set_resources(struct device *dev)
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{
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int idx;
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struct device *mc_dev;
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struct northbridge_amd_geodelx_pci_config *nb_pci =
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(struct northbridge_amd_geodelx_pci_config *)dev->device_configuration;
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printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
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@ -125,9 +160,9 @@ static void geodelx_pci_domain_set_resources(struct device *dev)
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idx = 10;
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/* 0 .. 640 KB */
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ram_resource(dev, idx++, 0, 640);
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/* 1 MB .. (Systop - 1 MB) (converted to KB) */
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/* 1 MB .. (Systop - 1 MB) (in KB) */
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ram_resource(dev, idx++, 1024,
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(get_systop() - (1 * 1024 * 1024)) / 1024);
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(get_systop(nb_pci)/1024) - 1024);
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}
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phase4_assign_resources(&dev->link[0]);
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@ -147,6 +182,9 @@ static void geodelx_pci_domain_set_resources(struct device *dev)
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*/
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static void geodelx_pci_domain_phase2(struct device *dev)
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{
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struct northbridge_amd_geodelx_pci_config *nb_pci =
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(struct northbridge_amd_geodelx_pci_config *)dev->device_configuration;
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void do_vsmbios(void);
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printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
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@ -161,8 +199,7 @@ static void geodelx_pci_domain_phase2(struct device *dev)
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printk(BIOS_SPEW, "After VSA:\n");
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/* print_conf(); */
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#warning graphics_init is disabled.
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/* graphics_init(); */
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graphics_init(nb_pci);
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pci_set_method(dev);
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}
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -23,63 +23,8 @@
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#include <msr.h>
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#include <cpu.h>
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#include <amd_geodelx.h>
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#include "geodelink.h"
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/* Function prototypes */
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struct gliutable {
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unsigned long desc_name;
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unsigned short desc_type;
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unsigned long hi, lo;
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};
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static struct gliutable gliu0table[] = {
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/* 0-7FFFF to MC */
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{.desc_name = MSR_GLIU0_BASE1,.desc_type = BM,.hi = MSR_MC + 0x0,
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.lo = 0x0FFF80},
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/* 80000-9FFFF to MC */
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{.desc_name = MSR_GLIU0_BASE2,.desc_type = BM,.hi = MSR_MC + 0x0,
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.lo = (0x80 << 20) + 0x0FFFE0},
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/* C0000-FFFFF split to MC and PCI (sub decode) A0000-BFFFF
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* handled by SoftVideo.
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*/
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{.desc_name = MSR_GLIU0_SHADOW,.desc_type = SC_SHADOW,
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.hi = MSR_MC + 0x0,.lo = 0x03},
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/* Catch and fix dynamically. */
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{.desc_name = MSR_GLIU0_SYSMEM,.desc_type = R_SYSMEM,
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.hi = MSR_MC,.lo = 0x0},
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/* Catch and fix dynamically. */
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{.desc_name = MSR_GLIU0_SMM,.desc_type = BMO_SMM,
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.hi = MSR_MC,.lo = 0x0},
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{.desc_name = GLIU0_GLD_MSR_COH,.desc_type = OTHER,
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.hi = 0x0,.lo = GL0_CPU},
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{.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},
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};
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static struct gliutable gliu1table[] = {
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/* 0-7FFFF to MC */
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{.desc_name = MSR_GLIU1_BASE1,.desc_type = BM,.hi = MSR_GL0 + 0x0,
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.lo = 0x0FFF80},
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/* 80000-9FFFF to MC */
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{.desc_name = MSR_GLIU1_BASE2,.desc_type = BM,.hi = MSR_GL0 + 0x0,
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.lo = (0x80 << 20) + 0x0FFFE0},
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/* C0000-Fffff split to MC and PCI (sub decode) */
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{.desc_name = MSR_GLIU1_SHADOW,.desc_type = SC_SHADOW,
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.hi = MSR_GL0 + 0x0,.lo = 0x03},
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/* Catch and fix dynamically. */
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{.desc_name = MSR_GLIU1_SYSMEM,.desc_type = R_SYSMEM,
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.hi = MSR_GL0,.lo = 0x0},
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/* Catch and fix dynamically. */
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{.desc_name = MSR_GLIU1_SMM,.desc_type = BM_SMM,
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.hi = MSR_GL0,.lo = 0x0},
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{.desc_name = GLIU1_GLD_MSR_COH,.desc_type = OTHER,
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.hi = 0x0,.lo = GL1_GLIU0},
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/* FooGlue FPU 0xF0 */
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{.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type = SCIO,
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.hi = (GL1_GLCP << 29) + 0x0,.lo = 0x033000F0},
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{.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},
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};
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static struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
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static struct msrinit clock_gating_default[] = {
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{GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
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@ -763,10 +708,6 @@ static void enable_L2_cache(void)
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printk(BIOS_DEBUG, "L2 cache enabled\n");
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}
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#ifndef CONFIG_VIDEO_MB
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#warning "CONFIG_VIDEO_MB was not defined"
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#define CONFIG_VIDEO_MB 8
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#endif
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/**
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* Set up all LX cache registers, L1, L2, and x86.
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@ -789,36 +730,6 @@ static void setup_lx_cache(void)
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__asm__("wbinvd\n"); /* TODO: Use wbinvd() function? */
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}
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/**
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* TODO.
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*
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* @return TODO.
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*/
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u32 get_systop(void)
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{
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struct gliutable *gl = NULL;
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u32 systop;
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struct msr msr;
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int i;
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for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
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if (gliu0table[i].desc_type == R_SYSMEM) {
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gl = &gliu0table[i];
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break;
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}
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}
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if (gl) {
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msr = rdmsr(gl->desc_name);
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systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8);
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systop += 4 * 1024; /* 4K */
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} else {
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systop =
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((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024;
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}
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return systop;
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}
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/**
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* Do all the Nasty Bits that have to happen.
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*
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62
northbridge/amd/geodelx/grphinit.c
Normal file
62
northbridge/amd/geodelx/grphinit.c
Normal file
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@ -0,0 +1,62 @@
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/*
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* This file is part of the coreboot project.
|
||||
*
|
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* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
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#include <io.h>
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#include <amd_geodelx.h>
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#include <console.h>
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#include <statictree.h>
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/*
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* This function mirrors the Graphics_Init routine in GeodeROM.
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*/
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void graphics_init(struct northbridge_amd_geodelx_pci_config *nb_pci)
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{
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u16 wClassIndex, wData, res;
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|
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/* SoftVG initialization */
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printk(BIOS_DEBUG, "Graphics init...\n");
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/* Call SoftVG with the main configuration parameters. */
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/* NOTE: SoftVG expects the memory size to be given in 2MB blocks */
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wClassIndex = (VRC_VG << 8) + VG_CONFIG;
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/*
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* Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP)
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* External Monochrome Card Support(12) 0, NO
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* Controller Priority Select(11) 1, Primary
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* Display Select(10:8) 0x0, CRT
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* Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1,
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* defined in mainboard/../dts
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* PLL Reference Clock Bypass(0) 0, Default
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*/
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/* Video RAM has to be given in 2MB chunks
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* the value is read @ 7:1 (looks like video_mb & ~1)
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* so we can add the real value in megabytes.
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||||
*/
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wData = VG_CFG_DRIVER | VG_CFG_PRIORITY |
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VG_CFG_DSCRT | (nb_pci->geode_video_mb & VG_MEM_MASK);
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vr_write(wClassIndex, wData);
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res = vr_read(wClassIndex);
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printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res);
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}
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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||||
*
|
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
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||||
*
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||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
@ -20,5 +21,8 @@
|
|||
|
||||
{
|
||||
device_operations = "geodelx_north_pci";
|
||||
|
||||
/* Video RAM has to be in 2MB chunks. */
|
||||
geode_video_mb = "0";
|
||||
};
|
||||
|
||||
|
|
Loading…
Add table
Reference in a new issue