it. Since it was the only content of the i440bxemulation northbridge
Kconfig, kill that file as well.
The i440BX RAM size is determined from the dts and the chipset specified
size is ignored. Print a warning for that, especially because v2 uses
the chipset specified RAM size.
Build and boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@766 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@765 f3766cd6-281f-0410-b1cd-43a5c92072e9
northbridge.c is marked for deletion, so don't sit up waiting for it to come home.
pci functions are in pci.c
domain functions are in domain.c
cpu functions are in cpu.c; cpu.c may move in the future to, say, someplace like cpu/amd/k8.
common functions are in common.c
These are still not set up quite right. I used svn copy to create the new files.
Geode builds fine. Anybody want to guess why this happens on k8? It's not clear to me.
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c: At top level:
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:60: error: ‘pci_conf1_read_config8’ redeclared as different kind of symbol
include/device/pci_ops.h:33: error: previous definition of ‘pci_conf1_read_config8’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:66: error: ‘pci_conf1_read_config16’ redeclared as different kind of symbol
include/device/pci_ops.h:34: error: previous definition of ‘pci_conf1_read_config16’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:72: error: ‘pci_conf1_read_config32’ redeclared as different kind of symbol
include/device/pci_ops.h:35: error: previous definition of ‘pci_conf1_read_config32’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:78: error: ‘pci_conf1_write_config8’ redeclared as different kind of symbol
include/device/pci_ops.h:36: error: previous definition of ‘pci_conf1_write_config8’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:84: error: ‘pci_conf1_write_config16’ redeclared as different kind of symbol
include/device/pci_ops.h:37: error: previous definition of ‘pci_conf1_write_config16’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:90: error: ‘pci_conf1_write_config32’ redeclared as different kind of symbol
include/device/pci_ops.h:38: error: previous definition of ‘pci_conf1_write_config32’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:116: error: ‘pci_conf1_find_on_bus’ redeclared as different kind of symbol
include/device/pci_ops.h:39: error: previous definition of ‘pci_conf1_find_on_bus’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:151: error: ‘pci_conf1_find_device’ redeclared as different kind of symbol
include/device/pci_ops.h:40: error: previous definition of ‘pci_conf1_find_device’ was here
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@764 f3766cd6-281f-0410-b1cd-43a5c92072e9
Remove stage1.h -- not needed.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@763 f3766cd6-281f-0410-b1cd-43a5c92072e9
This fixes a genuine bug in the MCP55 code.
Moving this away from PCI ops is the next goal.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@762 f3766cd6-281f-0410-b1cd-43a5c92072e9
arguably fixes some strange behaviour and prepares the code for
per-device subsystem ID setting.
It's the first step to achieve the per-device subsystem goal.
Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@761 f3766cd6-281f-0410-b1cd-43a5c92072e9
printk buffer management to it.
Build tested and boot tested and result tested on Qemu.
Adding a new global variable is not as easy as it looks, but the
comments in the code should be good enough to tell you how.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@760 f3766cd6-281f-0410-b1cd-43a5c92072e9
confusion when analyzing the logs. Improve readability.
This code may be obsolete, but that's not entriely sure yet.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@759 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: : Ronald G. Minnich <rminnich@gmail.com>
smbus_ops patched
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@758 f3766cd6-281f-0410-b1cd-43a5c92072e9
This changes SPD_NUM_COLUMNS from 0x8 back to 0xa, as it was originally when
copied over from another board, because 0x8 evaluates to 2kB, not 8kB, while 0xa
does the latter. 8kB is what the chip has and what is also set in our currently
used firmwares for DBE62.
This (combined with all the previous committed hard work from Ron before) fixes
memtest86+ freezes and hard reboots for me in quick 30 minute testing time,
while before it would freeze or reboot just into 50% of first test.
There is more to do to get the optimum RAM setup, but this should do for now -
the rest is just optimizing to quicker timings, while current ones in the fake
SPD are very conservative.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@757 f3766cd6-281f-0410-b1cd-43a5c92072e9
the system a bit so I am going to let this one get acked and I won't
push
any more patches until this goes through.
Add lpc support.
Make things compile lpc.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
And also:
That code is really buggy. I wonder how/if it ever worked in v2. If you
address the comments below, this is
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Comments (mostly) addressed. That said, I don't change functional code
that I know works -- we can fix that later. The ops_pci is addressed by
Carl-Daniel's patch.
git-svn-id: svn://coreboot.org/repository/coreboot-v3@756 f3766cd6-281f-0410-b1cd-43a5c92072e9
Basically, anything that includes files from include/ should define
STANDALONE, so that the includes don't try to created SHARED symbols.
This was not a problem until we made get_option SHARED.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@755 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@754 f3766cd6-281f-0410-b1cd-43a5c92072e9
Add a depend clause so that we don't see these things on Geode.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
The other changes are:
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@753 f3766cd6-281f-0410-b1cd-43a5c92072e9
all stages, blighting everything with the same code, compiled different
ways. In this change, we see that:
- basic conf ops are compiled into stage0, where they are used.
- they are called directly from initram
- they are used to initialize the pci_cf8_conf1 structure in stage 2,
but the call still goes to stage0!
one copy of the code.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@752 f3766cd6-281f-0410-b1cd-43a5c92072e9
This mirrors commit 3504 in coreboot v2.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@751 f3766cd6-281f-0410-b1cd-43a5c92072e9
The option code is tricky as it is used by standalone code. If you
include that file and you are standalone, you now have to define
STANDALONE (is there a better way?)
Change the cpuid to be a 24-byte string instead of 3 u32s.
Make the CPUID usage PIC-safe by not using %ebx.
Test building on two different geodes, tested to boot on dbe62
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@750 f3766cd6-281f-0410-b1cd-43a5c92072e9
Again, some of this is verbatim from v2, we can change the form later
please.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@749 f3766cd6-281f-0410-b1cd-43a5c92072e9
We will revisit it later.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@748 f3766cd6-281f-0410-b1cd-43a5c92072e9
These both compile. There is an unresolved issue w.r.t. the DEBUG
check in usb2. How do we want this in v3?
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@747 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
The other changes are:
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
I am well aware that those defines are not a great idea. I need some
good advice. I think we ought to have a stage1lib.c or something but
I'll take suggestions.
Thanks again
git-svn-id: svn://coreboot.org/repository/coreboot-v3@746 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@745 f3766cd6-281f-0410-b1cd-43a5c92072e9
This includes using consistent (C) lines, adding email addresses,
and so on. The file southbridge/nvidia/mcp55/dts was never edited
by Yinghai Lu (thus removing his (C) line) and would be too trivial
anyway...
The changes (though trivial) were also informally acked by Ron on IRC.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@744 f3766cd6-281f-0410-b1cd-43a5c92072e9
Add pci device. This compiles with no errors, no warnings.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
With the comments addressed:
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
I left the #if 1 in. It was there for a reason, we just don't know what it was.
I am reluctant to move such 'markers' at present.
git-svn-id: svn://coreboot.org/repository/coreboot-v3@741 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is managed by stripping the .dtc from the name when it
is used to label the node in the tree.
This one's for you Peter!
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@740 f3766cd6-281f-0410-b1cd-43a5c92072e9
add back in empty stage chipset variable. It will be filled in
later.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@736 f3766cd6-281f-0410-b1cd-43a5c92072e9
Modify all functions to use the new v3 pci operations calling conventions.
use udelay for delays.
Add the USB debug support function.
This is compiling pretty well for me save for the missing hypertransport function.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@731 f3766cd6-281f-0410-b1cd-43a5c92072e9
readability. Move to anonymous unions.
Build tested on all targets. Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ron tested this and it boots to Linux.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@730 f3766cd6-281f-0410-b1cd-43a5c92072e9
(1)we now compile in all printks, which is good: we can print any message provided we can change
the console log level at any time.
(2) The console log level is compiled in and unchangeable, which is bad, as it defeats the purpose of (1).
Add a BIOS_ALWAYS log level. Make console log level a variable. Make functions that set it and get it
visible everywhere. Always print out the version message; this is really *not* noise!
PCI: Simplify pci functions so that they can be used in stage1 or anywhere for that matter. Add
a find function which is needed for many stage1 functions. Note that we copy but also clean up
the libpayload stuff just a bit.
Get rid of config space type 2. If there was ever a platform that used it, I don't know what it was,
and the presence is a needless distraction.
tested and working on DBE62 (which means the console and the pci functions work :-).
There is a remaining problem with dumplxmsrs which nobody understands. It prints out garbage if we use the
%s for the msr names.
Formatting is an issue; if somebody wants to fix formatting they can assume I will ack it. Sorry,
my emacs has gone just nuts.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@729 f3766cd6-281f-0410-b1cd-43a5c92072e9
The problem was that gas treated whitespace asargument delimiter.
Removing the whitespace in crtitical places is the most obvious fix.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@727 f3766cd6-281f-0410-b1cd-43a5c92072e9
OPTIONS build/mainboard/gigabyte/m57sli/option_table.c
Error - Range end (122) does not match define (125) in line
checksum 392 983 984
cmos.layout did not conform to the requirements of the option table
creation code.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@726 f3766cd6-281f-0410-b1cd-43a5c92072e9
errata for early silicon and is not mentioned in the public rev guide.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@725 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@724 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@723 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@722 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@721 f3766cd6-281f-0410-b1cd-43a5c92072e9
Resource map and a way to use the pci config stuff from stage 1, done in
a way that will work in stage 2 (but only for systems that use type 1
config cycles; will fail for type MEM config cycles).
We need to rethink the PCI config stuff per Stepan's comment, in part
because the device tree now includes things that are NOT PCI devices.
Stepan's suggestion, to make the functions take busdevfn as the
parameter, makes a lot of sense.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.s
git-svn-id: svn://coreboot.org/repository/coreboot-v3@720 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@719 f3766cd6-281f-0410-b1cd-43a5c92072e9
it working, then we'll get it pretty.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@717 f3766cd6-281f-0410-b1cd-43a5c92072e9
