Commit graph

148 commits

Author SHA1 Message Date
Myles Watson
2b105d9bee This patch removes code related to PCI type 2 configuration cycles (gone as of
PCI 2.2)

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@982 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-05 22:18:53 +00:00
Ronald G. Minnich
07e50cd554 via vt8237, cn700 and jetway j7f2.
Does not yet build

Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@967 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-31 18:13:20 +00:00
Myles Watson
32139165ec This patch documents the unreadable function in northbridge/amd/k8/pci.c and
cleans up the NULL pointer protection.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@960 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-29 02:22:38 +00:00
Myles Watson
e7ea68860d Trivial fixes of printk \r\n and white space.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@958 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-28 17:29:07 +00:00
Myles Watson
345f5ac818 Trivial fixes of printk_debug and a comment from v2.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@957 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-28 16:06:28 +00:00
Ronald G. Minnich
cedf16ca69 Marc reviewed the v3 device tree code and we developed the set of
cleanups/fixes.

Fixup device tree code. Add/change methods as needed. 
This should help serengeti.
Signed-off-by: Ronald G. Minnich<rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@954 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-27 20:05:38 +00:00
Myles Watson
7bc7f67bfb This patch fixes whitespace so that a future patch is easier to read.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

Thanks,
Myles


git-svn-id: svn://coreboot.org/repository/coreboot-v3@953 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-24 19:26:34 +00:00
Myles Watson
7e654ac7a0 This patch fixes whitespace so that my next patch is easier to read.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

Thanks,
Myles


git-svn-id: svn://coreboot.org/repository/coreboot-v3@952 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-24 17:53:03 +00:00
Uwe Hermann
9b90a6f22b Fix a bunch of Doxygen warnings in v3 (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@951 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-23 18:55:01 +00:00
Uwe Hermann
aea512d5dc Coding-style, whitespace, and Doxygen-fixes for util.c (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@950 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-23 18:52:27 +00:00
Patrick Georgi
e0ab3a5564 Read actual memory size in qemu-i386
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@947 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-23 12:56:34 +00:00
Myles Watson
81b79f9052 This patch cleans up the showallroutes utility:
1. fix if->in in comments
2. change width of output for different types
3. make all masks 0x so that it's easy to tell a mask

It also changes the invocations to do function 1 instead of 0.

I think we should consider a name that makes it clear that this is only good
for AMD K8+ processors function 1.  We might need a similar utility for other
functions later. 

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@943 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-22 18:55:55 +00:00
Ronald G. Minnich
979bdb5ed0 Add functions to print routes.
I am totally convinced these are right. I am going on travel for a week 
and want these in your hands. 

Carl-Daniel as acked these, but for lack of time to get firefox going 
right now, 

Current serengeti output
DRAM(40)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(48)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(50)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(58)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(60)00000000-00ffffff, ->(4), , , No interleave, 0
DRAM(68)00000000-00ffffff, ->(0), R, W, 8 nodes, 0
DRAM(70)00000000-00ffffff, ->(0), , , No interleave, 0
DRAM(78)00000000-00ffffff, ->(0), , , No interleave, 0
MMIO(80)01a00000-1100ffff, ->(0,2), , , CPU disable 0, Lock 0, Non 
posted 0
MMIO(88)75060000-0000ffff, ->(2,0), , , CPU disable 0, Lock 0, Non 
posted 0
MMIO(90)51040000-3f00ffff, ->(0,0), , , CPU disable 1, Lock 0, Non 
posted 0
MMIO(98)00000000-0000ffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non 
posted 0
MMIO(a0)01c00000-1100ffff, ->(0,1), , , CPU disable 0, Lock 0, Non 
posted 1
MMIO(a8)75000000-0000ffff, ->(2,0), , , CPU disable 0, Lock 0, Non 
posted 0
MMIO(b0)51040000-0000ffff, ->(0,0), , , CPU disable 1, Lock 0, Non 
posted 0
MMIO(b8)00000000-0000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non 
posted 0
PCIIO(c0)00001010-00003110, ->(0,1), , ,VGA 0 ISA 0
PCIIO(c8)00000750-00000000, ->(2,0), , ,VGA 0 ISA 1
PCIIO(d0)00002510-00000000, ->(0,0), , ,VGA 1 ISA 0
PCIIO(d8)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0
CONFIG(e0)00000000-00000000 ->(0,0),  CE 0
CONFIG(e4)00000000-00000000 ->(0,0),  CE 0
CONFIG(e8)00000000-00000000 ->(0,0),  CE 0
CONFIG(ec)00000000-00000000 ->(0,0),  CE 0

Either the DRAM output is wrong or there is a real problem with our 
DRAM programming. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@941 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-21 03:20:05 +00:00
Corey Osgood
434a3816e0 Add ram init support for the Via CN700 to v3. Note that this isn't based on
current v2 support, but rather an older version I was working on that used too
many registers. It will be ported to v2 (eventually).

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@930 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-15 15:06:18 +00:00
Myles Watson
1dcad4bdd2 Change an ifdef to an ifndef so it matches the logic of v2. Clean up some
white space.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@927 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-14 16:31:57 +00:00
Ronald G. Minnich
8f8f14b136 Changes to make a get_nodes that can be built into stage1 and (for
m57sli) add incoherent ht chain support to stage1 as well. 

dbe62 was tested and works i.e. this does no harm.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@895 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-06 17:14:41 +00:00
Ronald G. Minnich
11c6d0d98d m57sli mostly builds again. The stage0 is too large at 24k.
We need to figure out if we should just grow stage0. My inclination is 
to say 'yes'.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@877 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-01 07:23:05 +00:00
Ronald G. Minnich
216231c0de Forgot to add this one.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@871 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-29 05:14:55 +00:00
Ronald G. Minnich
f2c21f5827 Continue cleanup. Still boots to etherboot in simnow.
Far fewer warnings than before :-)

TODO: Document the DIMM_SETTINGS variable. 
FIx up fidvid code. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@869 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-19 20:00:17 +00:00
Ronald G. Minnich
7ea90e1809 This set of changes adds new nodes to dts that are required, adds
some prints, and fixes a null pointer deref bug that has been in the 
k8 code since the dawn of time. 

We get here: 

CPU 804 Mhz
Etherboot 5.4.3 (GPL) http://etherboot.org
Drivers: VIA-VELOCITY/PCI   Images: ELF   
Protocols: DHCP TFTP 
Relocating _text from: [000100e0,000349c0) to [0007b720,000a0000)
Boot from (N)etwork or (Q)uit? 

Probing pci nic...
Probing isa nic...
<sleep>

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@867 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-18 16:45:46 +00:00
Ronald G. Minnich
28ecbeab88 The K8 is one example, but there are other devices (e.g. I2C) that also have
multiple links. The way this was done in v2 was a big confusing; this way is 
less so. 

The changes are easy. Getting them right has been hard :-)

First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0

We have to have the same pcidevfn on these because that is how the k8 works. 
But the unit numbers (pci0, pci1, etc.) distinguish them. 

The dts will properly generate a "v3 device code" 
compatible static tree that puts the links in the right place in the 
data structure. 

The changes to dts are trivial. 
As before, dts nodes with children are understood to be a bridge. 
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};


This entry has no children in the dts. 
How does dt compiler know it is a bridge? It can not know unless 
we add information to the dts for that northbridge part. 
To ensure that all bridge devices are detected, we support the following: 
if a dts node for a device has a bridge property, e.g.: 
 {
        device_operations = "k8_ops";
       bridge;
 };

The dt compiler will treat it as a bridge whether it has children or not. 

Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty, 
or what might be in the socket. 

This code has been tested on dbe62 and k8 simnow, and works on each. 
It is minimal in size and it does what we need. I hope it resolves our 
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!

Also included in this patch are new debug prints in k8 north. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-17 16:36:20 +00:00
Ronald G. Minnich
74e0a0a268 Make debug conditional.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@862 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-16 03:21:29 +00:00
Ronald G. Minnich
9cdd8a9d67 This finishes the fix to log2. The computed dram size now matches the
size indicated by byte 31 of SPD. 

Memory is still not working; hanging in dqs training. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@854 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-01 02:44:08 +00:00
Ronald G. Minnich
47043d7ab3 add some printks to raminit and correct a typo on one comment.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@851 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-31 02:46:37 +00:00
Ronald G. Minnich
ff2ddcb313 This gets us back to a compiling k8 target.
This code has been tested on dbe62, and builds for qemu as well. 

the next step is testing on simnow. 

k8.h: add more prototypes and some required inline functions. 
cpu.h: same
serengeti: expand defines in mainboard.h, though we need a better 
mechanism; continue to fix initram.c, add new support files to Makefile
lib/console.c: include globalvars.h
lib/lar.c: Provide more informative print as the lar is scanned.
k8 north: needed reset_test.c from v2, fixes to raminit.c
arch/x86
Kconfig: new CONFIG variable CBMEMK, meaning coreboot mem k, memory
	used for coreboot. 
init_cpus.c: functions to start up CPUs
stage1_mtrr.c: bring over early mtrr support from v2.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@847 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-30 03:35:40 +00:00
Ronald G. Minnich
f365719d09 This is closer! There are < 10 functions to be worked out, so most of
what you get are warnings. 

There is lots of room for improvement as we move to all CAR 
code, but that will take time. 

I hope to get this to really compile over the weekend. 

At the same time, if anybody wants to take a crack at it, your efforts
are welcome.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@843 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-29 04:33:56 +00:00
Ronald G. Minnich
fd31dee2a6 Closer to compiling. Add the fidvid functions. Continue to remove romcc
legacy. Use constants as much as possible instead of magic numbers. Set 
up common prototypes in an include file. 

The fidvid needs major cleanup but this code is so tricky I don't want 
to start cleanup until I feel it is more or less working. 

Signed-off-by: Ronald G. minnich <rminnich@gmail.com>
Acked-by: Ronald G. minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@841 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-28 17:14:04 +00:00
Ronald G. Minnich
96e0fd18bf Fixes to make k8 and others work.
We need the sys_info struct in the global variables struct for 
cache as ram on k8. The sys_info struct is generally very useful
so it makes sense to start accomodating it.  

This patch adds an (empty for now) sys_info struct for geode. 
It add sys_info to the global variables struct. 

It removes global variables from console.h to a new file, 
globalvars.h. Very little code needs to include this file. 

This patch is tested on the dbe62 and simnow with no problems.

k8 compilation is now broken but I'm working on it. I'm going through
the eyeballs-bleed code on k8 startup to document it and with any luck 
we'll have more functionality by the end of today. But it's hard ...

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@828 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-27 22:43:18 +00:00
Ronald G. Minnich
62f8ea8e9b This set of changes gets us much farther, in fact, we get into initram.
This means that basic resource maps are working, initial hypertransport 
setup is working, the amd8111 ISA device is working, config space is 
working for all the parts, we can grow the FLASH part address space to 
more than 64k, and in general we're having a good time. 

Here is the output:
coreboot-3.0.824 Tue Aug 26 22:18:21 PDT 2008 starting... 
(console_loglevel=8)
Choosing fallback boot.
LAR: Attempting to open 'fallback/initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: normal/option_table@0xfff80000, size 1776
LAR: normal/initram/segment0@0xfff80740, size 24404
LAR: normal/stage2/segment0@0xfff866f0, size 1
LAR: normal/stage2/segment1@0xfff86750, size 18542
LAR: normal/stage2/segment2@0xfff8b010, size 559
LAR: normal/payload/segment0@0xfff8b290, size 18142
LAR: bootblock@0xffff7fc0, size 32768
LAR: File not found!
LAR: Run file fallback/initram/segment0 failed: No such file.
Fallback failed. Try normal boot
LAR: Attempting to open 'normal/initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: normal/option_table@0xfff80000, size 1776
LAR: normal/initram/segment0@0xfff80740, size 24404
LAR: CHECK normal/initram/segment0 @ 0xfff80740
start 0xfff80790 len 24404 reallen 24404 compression 0 entry 0x00000004 
loadaddress 0x00000000
Entry point is 0xfff80794
Hi there from stage1
stage1 returns
run_file returns with 0

Goal for tomorrow is to get initram done. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@826 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-27 05:30:50 +00:00
Ronald G. Minnich
df78385663 1. Add call to stage 1 ht setup for mainboard
2. add support for same, brought over from v2.

Still no luck on 8111 ISA however. What are we missing?
The symptom is simple: Device 0:b.0 does not appear in the PCI list, so 
device with vid/did 1022/7468 is not there, so we can not enable 5 MiB 
flash addressing.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@824 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-26 22:12:02 +00:00
Ronald G. Minnich
7d7e653fce I can't believe I forgot all these.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@818 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-24 18:19:40 +00:00
Ronald G. Minnich
b2aa6a068d add libstage1.c
Remove pcspeaker until I can resolve space issues. Nobody was using it 
anyway as it happens. It will go back in as soon as we 
1. grow stage1 or
2. reconfigure it again

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@816 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-24 17:47:22 +00:00
Ronald G. Minnich
081602b211 More sensible way to conditionally include hypertransport.c
Builds both K8 and Geode bioses with no trouble.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnch <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@811 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-24 06:16:03 +00:00
Ronald G. Minnich
159354e6ba If you get a warning, it's because you SHOULD be getting a warning.
next step is to fix up this:
   LAR     build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error 
1
make: exit 2

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@809 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-24 03:27:28 +00:00
Ronald G. Minnich
f28a44eb48 This now compiles (with many warnings but ...) and tries to build a rom
image, and fails: 
  LAR     build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error 
1

Next step is to get rid of all warnings that are not #warning. 

Then it is on to simnow. 

Anyone who wants to work on the warnings is most welcome to. 

DBE62 still builds with no problems. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@808 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-24 02:59:05 +00:00
Ronald G. Minnich
784450567f This now compiles and has a simple error on build to stage2.
Geode still builds fine. 

include/lib.h includes a new function, cycles(), which is a u64 and 
architecture-defined. (Thanks, Plan 9, for a sensible idea). 

All rdtsc removed in favor of cycles()

All other changes are k8 specific. None of these changes adversely 
impact existing platforms AFAICT. 

Goal is that by 31/8/8, we're testing on simnow. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@807 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-23 16:51:00 +00:00
Carl-Daniel Hailfinger
87914c3169 The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of
code to use it. That makes the code more readable and also less
error-prone.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@805 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-22 18:24:53 +00:00
Ronald G. Minnich
b73481741f This is getting to the link phase. Still won't build as we don't have
dqs timing file compiled in yet. 

Per discussion with YingHai Lu, we are only going to support F2 and 
later CPUs. This will simplify more code. 

I realize this code needs work, but it is in v2, and cleanup will get 
easier once we have the baseline. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@804 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-22 16:48:44 +00:00
Carl-Daniel Hailfinger
88c1727722 i440bxemulation is missing the hole between 640k and 768k for VGA
(0xA0000-0xAFFFF) and text mode (0xB8000-0xBFFFF).

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@802 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-22 11:29:30 +00:00
Carl-Daniel Hailfinger
730c94aea0 Look for statictree.h in the standard search path.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@797 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-22 01:19:25 +00:00
Carl-Daniel Hailfinger
f1321e1ded Move GeodeLX register name array to .rodata and make my checker happy.
This one is far from obvious, so let me explain:
Basically, *msrnames[] is an array of pointers (strings) and pointers
need relocation. That's why they end up in .data.rel.ro.local and make
lots of trouble.
This should fix the crash Ron was seeing when register name printing was
enabled.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@793 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-21 17:34:06 +00:00
Ronald G. Minnich
4110e67004 Add ddr2 defines.
Continue to upgrade northbridge for k8. 

Add a new standard include (which is optional on some chipsets), 
mainboard.h, which will define important mainboard constants that
1. do not belong in dts
2. do not belong in Kconfig
3. are so tightly tied down to the mainboard they should probably not be 
visible, i.e. the value of the variable is defined by artwork on the 
mainboard, such as the socket type. 

This file resolves the long-standing question of where certain 
mainboard-dependent, compile-time control variables belong. 
We've not resolved this issue in two years so here's how 
we're going to do it. The first use of this is in the definition of 
CPU_SOCKET_TYPE, needed by the northbridge code. 

These changes do not affect existing Geode builds (tested on DBE62). 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@792 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-21 16:04:41 +00:00
Carl-Daniel Hailfinger
f7da69c7a9 Fix GeodeLX init variables in stage1 to be const. Real global
variables have to use the special framework or they won't work.

Found by my section correctness checker. Error message was:
  CHECK   stage0 (non-empty .data sections)
  build/northbridge/amd/geodelx/geodelxinit.o:
  geode_link_priority_table clock_gating_default

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@790 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-20 15:10:23 +00:00
Ronald G. Minnich
44d1585458 per discussion w/AMD, remove all conditionals based on REV_F.
It's all REV_F now and we're wasting time pretending otherwise. This 
change simplifies the code and will continue to simplify the code. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@788 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-18 20:31:34 +00:00
Ronald G. Minnich
7102949d76 We're much closer.
Added a stepping enum to k8.h. This will allow us to do things like this:
if (cpu_stepping(node) < E0)

and so on instead of is_cpu_pre_e0_in_bsp or whatever it is. 

Added and fixed Kconfig variables. 

Broke out northbridge by function, so we can see what goes with what. 

This tree still builds a working DBE62 coreboot that boots a kernel; no harm done to existing ports. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@781 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-17 22:18:09 +00:00
Carl-Daniel Hailfinger
1b3d2c1a0b stage1.h has been removed. Remove the corresponding include statement.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@769 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-15 19:23:11 +00:00
Carl-Daniel Hailfinger
fe0147c155 CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE was never used. Kill
it. Since it was the only content of the i440bxemulation northbridge
Kconfig, kill that file as well.
The i440BX RAM size is determined from the dts and the chipset specified
size is ignored. Print a warning for that, especially because v2 uses
the chipset specified RAM size.

Build and boot tested on qemu.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@766 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-15 16:41:37 +00:00
Ronald G. Minnich
8f3ad70a03 Continue cleaning up pci calls in stage1.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@765 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-14 17:00:11 +00:00
Ronald G. Minnich
e2a62b7e1d First cut at sanity in the northbridge. Break out functions so that there is some meaning to what is in what.
northbridge.c is marked for deletion, so don't sit up waiting for it to come home. 

pci functions are in pci.c

domain functions are in domain.c

cpu functions are in cpu.c; cpu.c may move in the future to, say, someplace like cpu/amd/k8. 

common functions are in common.c

These are still not set up quite right. I used svn copy to create the new files. 

Geode builds fine. Anybody want to guess why this happens on k8? It's not clear to me. 

/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c: At top level:
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:60: error: ‘pci_conf1_read_config8’ redeclared as different kind of symbol
include/device/pci_ops.h:33: error: previous definition of ‘pci_conf1_read_config8’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:66: error: ‘pci_conf1_read_config16’ redeclared as different kind of symbol
include/device/pci_ops.h:34: error: previous definition of ‘pci_conf1_read_config16’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:72: error: ‘pci_conf1_read_config32’ redeclared as different kind of symbol
include/device/pci_ops.h:35: error: previous definition of ‘pci_conf1_read_config32’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:78: error: ‘pci_conf1_write_config8’ redeclared as different kind of symbol
include/device/pci_ops.h:36: error: previous definition of ‘pci_conf1_write_config8’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:84: error: ‘pci_conf1_write_config16’ redeclared as different kind of symbol
include/device/pci_ops.h:37: error: previous definition of ‘pci_conf1_write_config16’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:90: error: ‘pci_conf1_write_config32’ redeclared as different kind of symbol
include/device/pci_ops.h:38: error: previous definition of ‘pci_conf1_write_config32’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:116: error: ‘pci_conf1_find_on_bus’ redeclared as different kind of symbol
include/device/pci_ops.h:39: error: previous definition of ‘pci_conf1_find_on_bus’ was here
/home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:151: error: ‘pci_conf1_find_device’ redeclared as different kind of symbol
include/device/pci_ops.h:40: error: previous definition of ‘pci_conf1_find_device’ was here
 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@764 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-14 16:31:24 +00:00
Carl-Daniel Hailfinger
209233d3f5 northbridge/amd/k8/get_sblk_pci1234.c license updated to GPL v2.
This mirrors commit 3504 in coreboot v2.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@751 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-12 23:54:25 +00:00