mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Add ddr2 defines.
Continue to upgrade northbridge for k8. Add a new standard include (which is optional on some chipsets), mainboard.h, which will define important mainboard constants that 1. do not belong in dts 2. do not belong in Kconfig 3. are so tightly tied down to the mainboard they should probably not be visible, i.e. the value of the variable is defined by artwork on the mainboard, such as the socket type. This file resolves the long-standing question of where certain mainboard-dependent, compile-time control variables belong. We've not resolved this issue in two years so here's how we're going to do it. The first use of this is in the definition of CPU_SOCKET_TYPE, needed by the northbridge code. These changes do not affect existing Geode builds (tested on DBE62). Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@792 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
parent
4bb450cfa3
commit
4110e67004
7 changed files with 2233 additions and 1327 deletions
|
@ -23,7 +23,7 @@
|
|||
ifeq ($(CONFIG_ARCH_X86),y)
|
||||
|
||||
INITCFLAGS := $(CFLAGS) -I$(src)/include/arch/x86 -I$(src)/include \
|
||||
-I$(obj) -fno-builtin
|
||||
-I$(obj) -I$(src)/mainboard/$(MAINBOARDDIR)/-fno-builtin
|
||||
|
||||
SILENT := >/dev/null 2>&1
|
||||
|
||||
|
@ -143,6 +143,10 @@ $(obj)/stage0.o $(obj)/stage0.init $(obj)/stage0-prefixed.o: $(STAGE0_OBJ)
|
|||
$(Q)# 0x4000 - 0x100, we will end up with a 4 gig file.
|
||||
$(Q)# I wonder if that behavior is on purpose.
|
||||
|
||||
$(Q)# .data and .bss must be empty because they aren't handled
|
||||
$(Q)printf " CHECK stage0 (non-empty writable/allocatable sections)\n"
|
||||
$(Q)./util/sectionchecker/sectionchecker objdump readelf $(STAGE0_OBJ)
|
||||
|
||||
$(Q)# Note: we invoke gcc (instead of ld directly) here, as we hit
|
||||
$(Q)# strange problems in the past. It seems that only gcc knows how
|
||||
$(Q)# to properly invoke ld.
|
||||
|
@ -264,6 +268,11 @@ $(obj)/arch/x86/amd/stage0.o: $(src)/arch/x86/amd/stage0.S
|
|||
$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_SRC)
|
||||
$(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n"
|
||||
$(Q)$(CC) $(INITCFLAGS) -fPIE -c -combine $(INITRAM_SRC) -o $(obj)/coreboot.initram_partiallylinked.o
|
||||
|
||||
$(Q)# .data and .bss must be empty because they aren't handled
|
||||
$(Q)printf " CHECK initram (non-empty writable/allocatable sections)\n"
|
||||
$(Q)./util/sectionchecker/sectionchecker objdump readelf $(obj)/coreboot.initram_partiallylinked.o
|
||||
|
||||
$(Q)printf " WRAP $(subst $(shell pwd)/,,$(@)) (PIC->non-PIC)\n"
|
||||
$(Q)$(NM) --undefined-only $(obj)/coreboot.initram_partiallylinked.o |\
|
||||
grep -v _GLOBAL_OFFSET_TABLE_ | grep " U " | sed "s/^ *U //" |\
|
||||
|
|
|
@ -23,6 +23,10 @@
|
|||
#define DIMM_SOCKETS 4
|
||||
#define NODE_NUMS 16
|
||||
|
||||
/* Socket types */
|
||||
#define SOCKET_AM2 0x11
|
||||
#define SOCKET_L1 0x10
|
||||
|
||||
#define ROM_CODE_SEG 0x08
|
||||
#define ROM_DATA_SEG 0x10
|
||||
|
||||
|
@ -59,8 +63,7 @@
|
|||
#define TOP_MEM_MASK 0x007fffff
|
||||
#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
|
||||
|
||||
|
||||
/* Definitions of various K8 registers */
|
||||
/* Definitions of various K8 registers for REV F*/
|
||||
/* Function 0 */
|
||||
#define HT_TRANSACTION_CONTROL 0x68
|
||||
#define HTTC_DIS_RD_B_P (1 << 0)
|
||||
|
@ -114,135 +117,349 @@
|
|||
#define DRAM_CSMASK 0x60
|
||||
#define DRAM_BANK_ADDR_MAP 0x80
|
||||
|
||||
#define DRAM_CTRL 0x78
|
||||
#define DC_RdPtrInit_SHIFT 0
|
||||
#define DC_RdPrtInit_MASK 0xf
|
||||
#define DC_RdPadRcvFifoDly_SHIFT 4
|
||||
#define DC_RdPadRcvFifoDly_MASK 7
|
||||
#define DC_RdPadRcvFiloDly_1_5_CLK 2
|
||||
#define DC_RdPadRcvFiloDly_2_CLK 3
|
||||
#define DC_RdPadRcvFiloDly_2_5_CLK 4
|
||||
#define DC_RdPadRcvFiloDly_3_CLK 5
|
||||
#define DC_RdPadRcvFiloDly_3_5_CLK 6
|
||||
#define DC_AltVidC3MemClkTriEn (1<<16)
|
||||
#define DC_DllTempAdjTime_SHIFT 17
|
||||
#define DC_DllTempAdjTime_MASK 1
|
||||
#define DC_DllTempAdjTime_5_MS 0
|
||||
#define DC_DllTempAdjTime_1_MS 1
|
||||
#define DC_DqsRcvEnTrain (1<<18)
|
||||
|
||||
#define DRAM_INIT 0x7c
|
||||
#define DI_MrsAddress_SHIFT 0
|
||||
#define DI_MrsAddress_MASK 0xffff
|
||||
#define DI_MrsBank_SHIFT 16
|
||||
#define DI_MrsBank_MASK 7
|
||||
#define DI_SendRchgAll (1<<24)
|
||||
#define DI_SendAutoRefresh (1<<25)
|
||||
#define DI_SendMrsCmd (1<<26)
|
||||
#define DI_DeassertMemRstX (1<<27)
|
||||
#define DI_AssertCke (1<<28)
|
||||
#define DI_EnDramInit (1<<31)
|
||||
|
||||
#define DRAM_TIMING_LOW 0x88
|
||||
#define DTL_TCL_SHIFT 0
|
||||
#define DTL_TCL_MASK 0x7
|
||||
#define DTL_CL_2 1
|
||||
#define DTL_CL_3 2
|
||||
#define DTL_CL_2_5 5
|
||||
#define DTL_TRC_SHIFT 4
|
||||
#define DTL_TRC_MASK 0xf
|
||||
#define DTL_TRC_BASE 7
|
||||
#define DTL_TRC_MIN 7
|
||||
#define DTL_TRC_MAX 22
|
||||
#define DTL_TRFC_SHIFT 8
|
||||
#define DTL_TRFC_MASK 0xf
|
||||
#define DTL_TRFC_BASE 9
|
||||
#define DTL_TRFC_MIN 9
|
||||
#define DTL_TRFC_MAX 24
|
||||
#define DTL_TRCD_SHIFT 12
|
||||
#define DTL_TRCD_MASK 0x7
|
||||
#define DTL_TRCD_BASE 0
|
||||
#define DTL_TRCD_MIN 2
|
||||
#define DTL_TRCD_MAX 6
|
||||
#define DTL_TRRD_SHIFT 16
|
||||
#define DTL_TRRD_MASK 0x7
|
||||
#define DTL_TRRD_BASE 0
|
||||
#define DTL_TRRD_MIN 2
|
||||
#define DTL_TRRD_MAX 4
|
||||
#define DTL_TRAS_SHIFT 20
|
||||
#define DTL_TCL_MASK 7
|
||||
#define DTL_TCL_BASE 1
|
||||
#define DTL_TCL_MIN 3
|
||||
#define DTL_TCL_MAX 6
|
||||
#define DTL_TRCD_SHIFT 4
|
||||
#define DTL_TRCD_MASK 3
|
||||
#define DTL_TRCD_BASE 3
|
||||
#define DTL_TRCD_MIN 3
|
||||
#define DTL_TRCD_MAX 6
|
||||
#define DTL_TRP_SHIFT 8
|
||||
#define DTL_TRP_MASK 3
|
||||
#define DTL_TRP_BASE 3
|
||||
#define DTL_TRP_MIN 3
|
||||
#define DTL_TRP_MAX 6
|
||||
#define DTL_TRTP_SHIFT 11
|
||||
#define DTL_TRTP_MASK 1
|
||||
#define DTL_TRTP_BASE 2
|
||||
#define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/
|
||||
#define DTL_TRTP_MAX 3 /* 5 for 64 bytes */
|
||||
#define DTL_TRAS_SHIFT 12
|
||||
#define DTL_TRAS_MASK 0xf
|
||||
#define DTL_TRAS_BASE 0
|
||||
#define DTL_TRAS_BASE 3
|
||||
#define DTL_TRAS_MIN 5
|
||||
#define DTL_TRAS_MAX 15
|
||||
#define DTL_TRP_SHIFT 24
|
||||
#define DTL_TRP_MASK 0x7
|
||||
#define DTL_TRP_BASE 0
|
||||
#define DTL_TRP_MIN 2
|
||||
#define DTL_TRP_MAX 6
|
||||
#define DTL_TWR_SHIFT 28
|
||||
#define DTL_TWR_MASK 0x1
|
||||
#define DTL_TWR_BASE 2
|
||||
#define DTL_TWR_MIN 2
|
||||
#define DTL_TWR_MAX 3
|
||||
#define DTL_TRAS_MAX 18
|
||||
#define DTL_TRC_SHIFT 16
|
||||
#define DTL_TRC_MASK 0xf
|
||||
#define DTL_TRC_BASE 11
|
||||
#define DTL_TRC_MIN 11
|
||||
#define DTL_TRC_MAX 26
|
||||
#define DTL_TWR_SHIFT 20
|
||||
#define DTL_TWR_MASK 3
|
||||
#define DTL_TWR_BASE 3
|
||||
#define DTL_TWR_MIN 3
|
||||
#define DTL_TWR_MAX 6
|
||||
#define DTL_TRRD_SHIFT 22
|
||||
#define DTL_TRRD_MASK 3
|
||||
#define DTL_TRRD_BASE 2
|
||||
#define DTL_TRRD_MIN 2
|
||||
#define DTL_TRRD_MAX 5
|
||||
#define DTL_MemClkDis_SHIFT 24 /* Channel A */
|
||||
#define DTL_MemClkDis3 (1 << 26)
|
||||
#define DTL_MemClkDis2 (1 << 27)
|
||||
#define DTL_MemClkDis1 (1 << 28)
|
||||
#define DTL_MemClkDis0 (1 << 29)
|
||||
#define DTL_MemClkDis1_AM2 (0x51 << 24)
|
||||
#define DTL_MemClkDis0_AM2 (0xa2 << 24)
|
||||
#define DTL_MemClkDis0_S1g1 (0xa2 << 24)
|
||||
|
||||
/* DTL_MemClkDis for m2 and s1g1 is different */
|
||||
|
||||
#define DRAM_TIMING_HIGH 0x8c
|
||||
#define DTH_TWTR_SHIFT 0
|
||||
#define DTH_TWTR_MASK 0x1
|
||||
#define DTH_TWTR_BASE 1
|
||||
#define DTH_TRWTTO_SHIFT 4
|
||||
#define DTH_TRWTTO_MASK 7
|
||||
#define DTH_TRWTTO_BASE 2
|
||||
#define DTH_TRWTTO_MIN 2
|
||||
#define DTH_TRWTTO_MAX 9
|
||||
#define DTH_TWTR_SHIFT 8
|
||||
#define DTH_TWTR_MASK 3
|
||||
#define DTH_TWTR_BASE 0
|
||||
#define DTH_TWTR_MIN 1
|
||||
#define DTH_TWTR_MAX 2
|
||||
#define DTH_TRWT_SHIFT 4
|
||||
#define DTH_TRWT_MASK 0x7
|
||||
#define DTH_TRWT_BASE 1
|
||||
#define DTH_TRWT_MIN 1
|
||||
#define DTH_TRWT_MAX 6
|
||||
#define DTH_TREF_SHIFT 8
|
||||
#define DTH_TREF_MASK 0x1f
|
||||
#define DTH_TREF_100MHZ_4K 0x00
|
||||
#define DTH_TREF_133MHZ_4K 0x01
|
||||
#define DTH_TREF_166MHZ_4K 0x02
|
||||
#define DTH_TREF_200MHZ_4K 0x03
|
||||
#define DTH_TREF_100MHZ_8K 0x08
|
||||
#define DTH_TREF_133MHZ_8K 0x09
|
||||
#define DTH_TREF_166MHZ_8K 0x0A
|
||||
#define DTH_TREF_200MHZ_8K 0x0B
|
||||
#define DTH_TWCL_SHIFT 20
|
||||
#define DTH_TWCL_MASK 0x7
|
||||
#define DTH_TWCL_BASE 1
|
||||
#define DTH_TWCL_MIN 1
|
||||
#define DTH_TWCL_MAX 2
|
||||
#define DTH_TWTR_MAX 3
|
||||
#define DTH_TWRRD_SHIFT 10
|
||||
#define DTH_TWRRD_MASK 3
|
||||
#define DTH_TWRRD_BASE 0
|
||||
#define DTH_TWRRD_MIN 0
|
||||
#define DTH_TWRRD_MAX 3
|
||||
#define DTH_TWRWR_SHIFT 12
|
||||
#define DTH_TWRWR_MASK 3
|
||||
#define DTH_TWRWR_BASE 1
|
||||
#define DTH_TWRWR_MIN 1
|
||||
#define DTH_TWRWR_MAX 3
|
||||
#define DTH_TRDRD_SHIFT 14
|
||||
#define DTH_TRDRD_MASK 3
|
||||
#define DTH_TRDRD_BASE 2
|
||||
#define DTH_TRDRD_MIN 2
|
||||
#define DTH_TRDRD_MAX 5
|
||||
#define DTH_TREF_SHIFT 16
|
||||
#define DTH_TREF_MASK 3
|
||||
#define DTH_TREF_7_8_US 2
|
||||
#define DTH_TREF_3_9_US 3
|
||||
#define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */
|
||||
#define DTH_TRFC_MASK 7
|
||||
#define DTH_TRFC_75_256M 0
|
||||
#define DTH_TRFC_105_512M 1
|
||||
#define DTH_TRFC_127_5_1G 2
|
||||
#define DTH_TRFC_195_2G 3
|
||||
#define DTH_TRFC_327_5_4G 4
|
||||
#define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */
|
||||
#define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */
|
||||
#define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */
|
||||
|
||||
#define DRAM_CONFIG_LOW 0x90
|
||||
#define DCL_DLL_Disable (1<<0)
|
||||
#define DCL_D_DRV (1<<1)
|
||||
#define DCL_QFC_EN (1<<2)
|
||||
#define DCL_DisDqsHys (1<<3)
|
||||
#define DCL_Burst2Opt (1<<5)
|
||||
#define DCL_DramInit (1<<8)
|
||||
#define DCL_DualDIMMen (1<<9)
|
||||
#define DCL_DramEnable (1<<10)
|
||||
#define DCL_MemClrStatus (1<<11)
|
||||
#define DCL_ESR (1<<12)
|
||||
#define DCL_SRS (1<<13)
|
||||
#define DCL_128BitEn (1<<16)
|
||||
#define DCL_DimmEccEn (1<<17)
|
||||
#define DCL_UnBufDimm (1<<18)
|
||||
#define DCL_32ByteEn (1<<19)
|
||||
#define DCL_x4DIMM_SHIFT 20
|
||||
#define DCL_DisInRcvrs (1<<24)
|
||||
#define DCL_BypMax_SHIFT 25
|
||||
#define DCL_En2T (1<<28)
|
||||
#define DCL_UpperCSMap (1<<29)
|
||||
|
||||
#define DCL_InitDram (1<<0)
|
||||
#define DCL_ExitSelfRef (1<<1)
|
||||
#define DCL_DramTerm_SHIFT 4
|
||||
#define DCL_DramTerm_MASK 3
|
||||
#define DCL_DramTerm_No 0
|
||||
#define DCL_DramTerm_75_OH 1
|
||||
#define DCL_DramTerm_150_OH 2
|
||||
#define DCL_DramTerm_50_OH 3
|
||||
#define DCL_DrvWeak (1<<7)
|
||||
#define DCL_ParEn (1<<8)
|
||||
#define DCL_SelfRefRateEn (1<<9)
|
||||
#define DCL_BurstLength32 (1<<10)
|
||||
#define DCL_Width128 (1<<11)
|
||||
#define DCL_X4Dimm_SHIFT 12
|
||||
#define DCL_X4Dimm_MASK 0xf
|
||||
#define DCL_UnBuffDimm (1<<16)
|
||||
#define DCL_DimmEccEn (1<<19)
|
||||
|
||||
#define DRAM_CONFIG_HIGH 0x94
|
||||
#define DCH_ASYNC_LAT_SHIFT 0
|
||||
#define DCH_ASYNC_LAT_MASK 0xf
|
||||
#define DCH_ASYNC_LAT_BASE 0
|
||||
#define DCH_ASYNC_LAT_MIN 0
|
||||
#define DCH_ASYNC_LAT_MAX 15
|
||||
#define DCH_RDPREAMBLE_SHIFT 8
|
||||
#define DCH_RDPREAMBLE_MASK 0xf
|
||||
#define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */
|
||||
#define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */
|
||||
#define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */
|
||||
#define DCH_IDLE_LIMIT_SHIFT 16
|
||||
#define DCH_IDLE_LIMIT_MASK 0x7
|
||||
#define DCH_IDLE_LIMIT_0 0
|
||||
#define DCH_IDLE_LIMIT_4 1
|
||||
#define DCH_IDLE_LIMIT_8 2
|
||||
#define DCH_IDLE_LIMIT_16 3
|
||||
#define DCH_IDLE_LIMIT_32 4
|
||||
#define DCH_IDLE_LIMIT_64 5
|
||||
#define DCH_IDLE_LIMIT_128 6
|
||||
#define DCH_IDLE_LIMIT_256 7
|
||||
#define DCH_DYN_IDLE_CTR_EN (1 << 19)
|
||||
#define DCH_MEMCLK_SHIFT 20
|
||||
#define DCH_MEMCLK_MASK 0x7
|
||||
#define DCH_MEMCLK_100MHZ 0
|
||||
#define DCH_MEMCLK_133MHZ 2
|
||||
#define DCH_MEMCLK_166MHZ 5
|
||||
#define DCH_MEMCLK_200MHZ 7
|
||||
#define DCH_MEMCLK_VALID (1 << 25)
|
||||
#define DCH_MEMCLK_EN0 (1 << 26)
|
||||
#define DCH_MEMCLK_EN1 (1 << 27)
|
||||
#define DCH_MEMCLK_EN2 (1 << 28)
|
||||
#define DCH_MEMCLK_EN3 (1 << 29)
|
||||
#define DCH_MemClkFreq_SHIFT 0
|
||||
#define DCH_MemClkFreq_MASK 7
|
||||
#define DCH_MemClkFreq_200MHz 0
|
||||
#define DCH_MemClkFreq_266MHz 1
|
||||
#define DCH_MemClkFreq_333MHz 2
|
||||
#define DCH_MemClkFreq_400MHz 3
|
||||
#define DCH_MemClkFreqVal (1<<3)
|
||||
#define DCH_MaxAsyncLat_SHIFT 4
|
||||
#define DCH_MaxAsyncLat_MASK 0xf
|
||||
#define DCH_MaxAsyncLat_BASE 0
|
||||
#define DCH_MaxAsyncLat_MIN 0
|
||||
#define DCH_MaxAsyncLat_MAX 15
|
||||
#define DCH_RDqsEn (1<<12)
|
||||
#define DCH_DisDramInterface (1<<14)
|
||||
#define DCH_PowerDownEn (1<<15)
|
||||
#define DCH_PowerDownMode_SHIFT 16
|
||||
#define DCH_PowerDownMode_MASK 1
|
||||
#define DCH_PowerDownMode_Channel_CKE 0
|
||||
#define DCH_PowerDownMode_ChipSelect_CKE 1
|
||||
#define DCH_FourRankSODimm (1<<17)
|
||||
#define DCH_FourRankRDimm (1<<18)
|
||||
#define DCH_SlowAccessMode (1<<19)
|
||||
#define DCH_BankSwizzleMode (1<<22)
|
||||
#define DCH_DcqBypassMax_SHIFT 24
|
||||
#define DCH_DcqBypassMax_MASK 0xf
|
||||
#define DCH_DcqBypassMax_BASE 0
|
||||
#define DCH_DcqBypassMax_MIN 0
|
||||
#define DCH_DcqBypassMax_MAX 15
|
||||
#define DCH_FourActWindow_SHIFT 28
|
||||
#define DCH_FourActWindow_MASK 0xf
|
||||
#define DCH_FourActWindow_BASE 7
|
||||
#define DCH_FourActWindow_MIN 8
|
||||
#define DCH_FourActWindow_MAX 20
|
||||
|
||||
|
||||
// for 0x98 index and 0x9c data
|
||||
#define DRAM_CTRL_ADDI_DATA_OFFSET 0x98
|
||||
#define DCAO_DctOffset_SHIFT 0
|
||||
#define DCAO_DctOffset_MASK 0x3fffffff
|
||||
#define DCAO_DctAccessWrite (1<<30)
|
||||
#define DCAO_DctAccessDone (1<<31)
|
||||
|
||||
#define DRAM_CTRL_ADDI_DATA_PORT 0x9c
|
||||
|
||||
#define DRAM_OUTPUT_DRV_COMP_CTRL 0x00
|
||||
#define DODCC_CkeDrvStren_SHIFT 0
|
||||
#define DODCC_CkeDrvStren_MASK 3
|
||||
#define DODCC_CkeDrvStren_1_0X 0
|
||||
#define DODCC_CkeDrvStren_1_25X 1
|
||||
#define DODCC_CkeDrvStren_1_5X 2
|
||||
#define DODCC_CkeDrvStren_2_0X 3
|
||||
#define DODCC_CsOdtDrvStren_SHIFT 4
|
||||
#define DODCC_CsOdtDrvStren_MASK 3
|
||||
#define DODCC_CsOdtDrvStren_1_0X 0
|
||||
#define DODCC_CsOdtDrvStren_1_25X 1
|
||||
#define DODCC_CsOdtDrvStren_1_5X 2
|
||||
#define DODCC_CsOdtDrvStren_2_0X 3
|
||||
#define DODCC_AddrCmdDrvStren_SHIFT 8
|
||||
#define DODCC_AddrCmdDrvStren_MASK 3
|
||||
#define DODCC_AddrCmdDrvStren_1_0X 0
|
||||
#define DODCC_AddrCmdDrvStren_1_25X 1
|
||||
#define DODCC_AddrCmdDrvStren_1_5X 2
|
||||
#define DODCC_AddrCmdDrvStren_2_0X 3
|
||||
#define DODCC_ClkDrvStren_SHIFT 12
|
||||
#define DODCC_ClkDrvStren_MASK 3
|
||||
#define DODCC_ClkDrvStren_0_75X 0
|
||||
#define DODCC_ClkDrvStren_1_0X 1
|
||||
#define DODCC_ClkDrvStren_1_25X 2
|
||||
#define DODCC_ClkDrvStren_1_5X 3
|
||||
#define DODCC_DataDrvStren_SHIFT 16
|
||||
#define DODCC_DataDrvStren_MASK 3
|
||||
#define DODCC_DataDrvStren_0_75X 0
|
||||
#define DODCC_DataDrvStren_1_0X 1
|
||||
#define DODCC_DataDrvStren_1_25X 2
|
||||
#define DODCC_DataDrvStren_1_5X 3
|
||||
#define DODCC_DqsDrvStren_SHIFT 20
|
||||
#define DODCC_DqsDrvStren_MASK 3
|
||||
#define DODCC_DqsDrvStren_0_75X 0
|
||||
#define DODCC_DqsDrvStren_1_0X 1
|
||||
#define DODCC_DqsDrvStren_1_25X 2
|
||||
#define DODCC_DqsDrvStren_1_5X 3
|
||||
#define DODCC_ProcOdt_SHIFT 28
|
||||
#define DODCC_ProcOdt_MASK 3
|
||||
#define DODCC_ProcOdt_300_OHMS 0
|
||||
#define DODCC_ProcOdt_150_OHMS 1
|
||||
#define DODCC_ProcOdt_75_OHMS 2
|
||||
|
||||
#define DRAM_WRITE_DATA_TIMING_CTRL_LOW 0x01
|
||||
#define DWDTCL_WrDatTimeByte0_SHIFT 0
|
||||
#define DWDTC_WrDatTimeByte_MASK 0x3f
|
||||
#define DWDTC_WrDatTimeByte_BASE 0
|
||||
#define DWDTC_WrDatTimeByte_MIN 0
|
||||
#define DWDTC_WrDatTimeByte_MAX 47
|
||||
#define DWDTCL_WrDatTimeByte1_SHIFT 8
|
||||
#define DWDTCL_WrDatTimeByte2_SHIFT 16
|
||||
#define DWDTCL_WrDatTimeByte3_SHIFT 24
|
||||
|
||||
#define DRAM_WRITE_DATA_TIMING_CTRL_HIGH 0x02
|
||||
#define DWDTCH_WrDatTimeByte4_SHIFT 0
|
||||
#define DWDTCH_WrDatTimeByte5_SHIFT 8
|
||||
#define DWDTCH_WrDatTimeByte6_SHIFT 16
|
||||
#define DWDTCH_WrDatTimeByte7_SHIFT 24
|
||||
|
||||
#define DRAM_WRITE_DATA_ECC_TIMING_CTRL 0x03
|
||||
#define DWDETC_WrChkTime_SHIFT 0
|
||||
#define DWDETC_WrChkTime_MASK 0x3f
|
||||
#define DWDETC_WrChkTime_BASE 0
|
||||
#define DWDETC_WrChkTime_MIN 0
|
||||
#define DWDETC_WrChkTime_MAX 47
|
||||
|
||||
#define DRAM_ADDR_TIMING_CTRL 0x04
|
||||
#define DATC_CkeFineDelay_SHIFT 0
|
||||
#define DATC_CkeFineDelay_MASK 0x1f
|
||||
#define DATC_CkeFineDelay_BASE 0
|
||||
#define DATC_CkeFineDelay_MIN 0
|
||||
#define DATC_CkeFineDelay_MAX 31
|
||||
#define DATC_CkeSetup (1<<5)
|
||||
#define DATC_CsOdtFineDelay_SHIFT 8
|
||||
#define DATC_CsOdtFineDelay_MASK 0x1f
|
||||
#define DATC_CsOdtFineDelay_BASE 0
|
||||
#define DATC_CsOdtFineDelay_MIN 0
|
||||
#define DATC_CsOdtFineDelay_MAX 31
|
||||
#define DATC_CsOdtSetup (1<<13)
|
||||
#define DATC_AddrCmdFineDelay_SHIFT 16
|
||||
#define DATC_AddrCmdFineDelay_MASK 0x1f
|
||||
#define DATC_AddrCmdFineDelay_BASE 0
|
||||
#define DATC_AddrCmdFineDelay_MIN 0
|
||||
#define DATC_AddrCmdFineDelay_MAX 31
|
||||
#define DATC_AddrCmdSetup (1<<21)
|
||||
|
||||
#define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05
|
||||
#define DRDTCL_RdDqsTimeByte0_SHIFT 0
|
||||
#define DRDTC_RdDqsTimeByte_MASK 0x3f
|
||||
#define DRDTC_RdDqsTimeByte_BASE 0
|
||||
#define DRDTC_RdDqsTimeByte_MIN 0
|
||||
#define DRDTC_RdDqsTimeByte_MAX 47
|
||||
#define DRDTCL_RdDqsTimeByte1_SHIFT 8
|
||||
#define DRDTCL_RdDqsTimeByte2_SHIFT 16
|
||||
#define DRDTCL_RdDqsTimeByte3_SHIFT 24
|
||||
|
||||
#define DRAM_READ_DQS_TIMING_CTRL_HIGH 0x06
|
||||
#define DRDTCH_RdDqsTimeByte4_SHIFT 0
|
||||
#define DRDTCH_RdDqsTimeByte5_SHIFT 8
|
||||
#define DRDTCH_RdDqsTimeByte6_SHIFT 16
|
||||
#define DRDTCH_RdDqsTimeByte7_SHIFT 24
|
||||
|
||||
#define DRAM_READ_DQS_ECC_TIMING_CTRL 0x07
|
||||
#define DRDETC_RdDqsTimeCheck_SHIFT 0
|
||||
#define DRDETC_RdDqsTimeCheck_MASK 0x3f
|
||||
#define DRDETC_RdDqsTimeCheck_BASE 0
|
||||
#define DRDETC_RdDqsTimeCheck_MIN 0
|
||||
#define DRDETC_RdDqsTimeCheck_MAX 47
|
||||
|
||||
#define DRAM_DQS_RECV_ENABLE_TIME0 0x10
|
||||
#define DDRET_DqsRcvEnDelay_SHIFT 0
|
||||
#define DDRET_DqsRcvEnDelay_MASK 0xff
|
||||
#define DDRET_DqsRcvEnDelay_BASE 0
|
||||
#define DDRET_DqsRcvEnDelay_MIN 0
|
||||
#define DDRET_DqsRcvEnDelay_MAX 0xae /* unit is 50ps */
|
||||
|
||||
#define DRAM_DQS_RECV_ENABLE_TIME1 0x13
|
||||
#define DRAM_DQS_RECV_ENABLE_TIME2 0x16
|
||||
#define DRAM_DQS_RECV_ENABLE_TIME3 0x19
|
||||
|
||||
/* there are index 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39
|
||||
that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, 0x13, 0x16, 0x19
|
||||
*/
|
||||
#define DRAM_CTRL_MISC 0xa0
|
||||
#define DCM_MemClrStatus (1<<0)
|
||||
#define DCM_DisableJitter (1<<1)
|
||||
#define DCM_RdWrQByp_SHIFT 2
|
||||
#define DCM_RdWrQByp_MASK 3
|
||||
#define DCM_RdWrQByp_2 0
|
||||
#define DCM_RdWrQByp_4 1
|
||||
#define DCM_RdWrQByp_8 2
|
||||
#define DCM_RdWrQByp_16 3
|
||||
#define DCM_Mode64BitMux (1<<4)
|
||||
#define DCM_DCC_EN (1<<5)
|
||||
#define DCM_ILD_lmt_SHIFT 6
|
||||
#define DCM_ILD_lmt_MASK 7
|
||||
#define DCM_ILD_lmt_0 0
|
||||
#define DCM_ILD_lmt_4 1
|
||||
#define DCM_ILD_lmt_8 2
|
||||
#define DCM_ILD_lmt_16 3
|
||||
#define DCM_ILD_lmt_32 4
|
||||
#define DCM_ILD_lmt_64 5
|
||||
#define DCM_ILD_lmt_128 6
|
||||
#define DCM_ILD_lmt_256 7
|
||||
#define DCM_DramEnabled (1<<9)
|
||||
#define DCM_MemClkDis_SHIFT 24 /* Channel B */
|
||||
#define DCM_MemClkDis3 (1 << 26)
|
||||
#define DCM_MemClkDis2 (1 << 27)
|
||||
#define DCM_MemClkDis1 (1 << 28)
|
||||
#define DCM_MemClkDis0 (1 << 29)
|
||||
|
||||
|
||||
/* Function 3 */
|
||||
#define MCA_NB_CONFIG 0x44
|
||||
#define MNC_ECC_EN (1 << 22)
|
||||
#define MNC_CHIPKILL_EN (1 << 23)
|
||||
|
||||
#define SCRUB_CONTROL 0x58
|
||||
#define SCRUB_NONE 0
|
||||
#define SCRUB_40ns 1
|
||||
|
@ -273,8 +490,11 @@
|
|||
#define SC_L2_SCRUB_RATE_MASK 0x1f
|
||||
#define SC_L1D_SCRUB_RATE_SHIFT 16
|
||||
#define SC_L1D_SCRUB_RATE_MASK 0x1f
|
||||
|
||||
#define SCRUB_ADDR_LOW 0x5C
|
||||
|
||||
#define SCRUB_ADDR_HIGH 0x60
|
||||
|
||||
#define NORTHBRIDGE_CAP 0xE8
|
||||
#define NBCAP_128Bit (1 << 0)
|
||||
#define NBCAP_MP (1 << 1)
|
||||
|
@ -283,20 +503,15 @@
|
|||
#define NBCAP_CHIPKILL_ECC (1 << 4)
|
||||
#define NBCAP_MEMCLK_SHIFT 5
|
||||
#define NBCAP_MEMCLK_MASK 3
|
||||
#define NBCAP_MEMCLK_100MHZ 3
|
||||
#define NBCAP_MEMCLK_133MHZ 2
|
||||
#define NBCAP_MEMCLK_166MHZ 1
|
||||
#define NBCAP_MEMCLK_200MHZ 0
|
||||
#define NBCAP_MEMCLK_200MHZ 3
|
||||
#define NBCAP_MEMCLK_266MHZ 2
|
||||
#define NBCAP_MEMCLK_333MHZ 1
|
||||
#define NBCAP_MEMCLK_NOLIMIT 0
|
||||
#define NBCAP_MEMCTRL (1 << 8)
|
||||
#define NBCAP_HtcCap (1<<10)
|
||||
#define NBCAP_CmpCap_SHIFT 12
|
||||
#define NBCAP_CmpCap_MASK 3
|
||||
|
||||
/* resources for the routing in the northbridge. These may be family specific;
|
||||
* the were in v2.
|
||||
*/
|
||||
#define RES_DEBUG 0
|
||||
#define RES_PCI_IO 0x10
|
||||
#define RES_PORT_IO_8 0x22
|
||||
#define RES_PORT_IO_32 0x20
|
||||
#define RES_MEM_IO 0x40
|
||||
|
||||
#define LinkConnected (1 << 0)
|
||||
#define InitComplete (1 << 1)
|
||||
|
|
88
include/spd_ddr2.h
Normal file
88
include/spd_ddr2.h
Normal file
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* SPDs for DDR2 SDRAM */
|
||||
#define SPD_MEM_TYPE 2
|
||||
#define SPD_MEM_TYPE_SDRAM_DDR 0x07
|
||||
#define SPD_MEM_TYPE_SDRAM_DDR2 0x08
|
||||
|
||||
#define SPD_DIMM_TYPE 20 /* x bit0 or bit4 =1 mean registered*/
|
||||
#define SPD_DIMM_TYPE_RDIMM (1<<0)
|
||||
#define SPD_DIMM_TYPE_UDIMM (1<<1)
|
||||
#define SPD_DIMM_TYPE_SODIMM (1<<2)
|
||||
#define SPD_DIMM_TYPE_uDIMM (1<<3)
|
||||
#define SPD_DIMM_TYPE_mRDIMM (1<<4)
|
||||
#define SPD_DIMM_TYPE_mUDIMM (1<<5)
|
||||
#define SPD_MOD_ATTRIB 21
|
||||
#define SPD_MOD_ATTRIB_DIFCK 0x20
|
||||
#define SPD_MOD_ATTRIB_REGADC 0x11 /* x */
|
||||
#define SPD_MOD_ATTRIB_PROBE 0x40
|
||||
|
||||
#define SPD_DEV_ATTRIB 22 /* Device attributes --- general */
|
||||
#define SPD_DIMM_CONF_TYPE 11
|
||||
#define SPD_DIMM_CONF_TYPE_ECC 0x02
|
||||
#define SPD_DIMM_CONF_TYPE_ADDR_PARITY 0x04 /* ? */
|
||||
|
||||
#define SPD_ROW_NUM 3 /* Number of Row addresses */
|
||||
#define SPD_COL_NUM 4 /* Number of Column addresses */
|
||||
#define SPD_BANK_NUM 17 /* SDRAM Device attributes - Number of Banks on
|
||||
SDRAM device, it could be 0x4, 0x8, so address
|
||||
lines for that would be 2, and 3 */
|
||||
|
||||
/* Number of Ranks bit [2:0], Package (bit4, 1=stack, 0=planr), Height bit[7:5] */
|
||||
#define SPD_MOD_ATTRIB_RANK 5
|
||||
#define SPD_MOD_ATTRIB_RANK_NUM_SHIFT 0
|
||||
#define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07
|
||||
#define SPD_MOD_ATTRIB_RANK_NUM_BASE 1
|
||||
#define SPD_MOD_ATTRIB_RANK_NUM_MIN 1
|
||||
#define SPD_MOD_ATTRIB_RANK_NUM_MAX 8
|
||||
|
||||
#define SPD_RANK_SIZE 31 /* Only one bit is set */
|
||||
#define SPD_RANK_SIZE_1GB (1<<0)
|
||||
#define SPD_RANK_SIZE_2GB (1<<1)
|
||||
#define SPD_RANK_SIZE_4GB (1<<2)
|
||||
#define SPD_RANK_SIZE_8GB (1<<3)
|
||||
#define SPD_RANK_SIZE_16GB (1<<4)
|
||||
#define SPD_RANK_SIZE_128MB (1<<5)
|
||||
#define SPD_RANK_SIZE_256MB (1<<6)
|
||||
#define SPD_RANK_SIZE_512MB (1<<7)
|
||||
|
||||
#define SPD_DATA_WIDTH 6 /* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */
|
||||
#define SPD_PRI_WIDTH 13 /* Primary SDRAM Width, it could be 0x08 or 0x10 */
|
||||
#define SPD_ERR_WIDTH 14 /* Error Checking SDRAM Width, it could be 0x08 or 0x10 */
|
||||
|
||||
#define SPD_CAS_LAT 18 /* SDRAM Device Attributes -- CAS Latency */
|
||||
#define SPD_CAS_LAT_2 (1<<2)
|
||||
#define SPD_CAS_LAT_3 (1<<3)
|
||||
#define SPD_CAS_LAT_4 (1<<4)
|
||||
#define SPD_CAS_LAT_5 (1<<5)
|
||||
#define SPD_CAS_LAT_6 (1<<6)
|
||||
|
||||
#define SPD_TRP 27 /* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) + (val & 3) * 0.25)ns */
|
||||
#define SPD_TRRD 28
|
||||
#define SPD_TRCD 29
|
||||
#define SPD_TRAS 30
|
||||
#define SPD_TWR 36 /* x */
|
||||
#define SPD_TWTR 37 /* x */
|
||||
#define SPD_TRTP 38 /* x */
|
||||
|
||||
#define SPD_TRC 41 /* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}*/
|
||||
#define SPD_TRFC 42 /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] + (val40 & 1)*256*/
|
||||
|
||||
#define SPD_TREF 12
|
|
@ -52,9 +52,7 @@ config BOARD_AMD_SERENGETI
|
|||
select OPTION_TABLE
|
||||
select CPU_AMD_K8
|
||||
select NORTHBRIDGE_AMD_K8
|
||||
select SOUTHBRIDGE_AMD_AMD8111
|
||||
select IOAPIC
|
||||
select APIC_ID_OFFSET
|
||||
help
|
||||
AMD Serengeti
|
||||
|
||||
|
|
24
mainboard/amd/serengeti/mainboard.h
Normal file
24
mainboard/amd/serengeti/mainboard.h
Normal file
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
* Constants that are mainboard-defined and do not belong in Kconfig.
|
||||
* We really do not want this stuff to be visible -- it will make it appear that they can be
|
||||
* changed, and they can not.
|
||||
*
|
||||
* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define CPU_SOCKET_TYPE SOCKET_AM2
|
|
@ -52,7 +52,7 @@ void dumplxmsrs(void)
|
|||
MC_CF_PMCTR,
|
||||
GLCP_SYS_RSTPLL
|
||||
};
|
||||
const static char *msrnames[] = {
|
||||
const static const char *msrnames[] = {
|
||||
"MC_CF07_DATA",
|
||||
"MC_CF8F_DATA",
|
||||
"MC_CF1017_DATA",
|
||||
|
|
File diff suppressed because it is too large
Load diff
Loading…
Add table
Reference in a new issue