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per discussion w/AMD, remove all conditionals based on REV_F.

Browse source 
It's all REV_F now and we're wasting time pretending otherwise. This 
change simplifies the code and will continue to simplify the code. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@788 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-08-18 20:31:34 +00:00
parent c407b9e1e0
commit 44d1585458
8 changed files with 16 additions and 142 deletions
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8
device/hypertransport.c
View file

@ -95,13 +95,7 @@ static unsigned ht_read_freq_cap(struct device *dev, unsigned pos)
}
/* AMD K8 unsupported 1GHz? */
if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) {
#if K8_HT_FREQ_1G_SUPPORT == 1
#if K8_REV_F_SUPPORT == 0
if (is_cpu_pre_e0()) { // Only e0 later support 1GHz HT.
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
}
#endif
#else
#ifndef K8_HT_FREQ_1G_SUPPORT
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
#endif

62
include/arch/x86/amd/k8/k8.h
View file

@ -306,60 +306,16 @@
#ifndef ASSEMBLY
/* Steppings of the K8 cpu */
enum steppings {
A0,
A1,
A2,
B0,
C0,
CG,
enum {
A0= 0x0f00,
B3= 0x0f41,
C0= 0x0f48,
CG, /* value not yet known */
D0= 0x10f00,
E0= 0x20f00,
F0= 0x40f00,
F2= 0x40f02,
};
/* cpu version -- no support for f0 yet */
static inline int is_cpu_rev_a0(void)
{
return (cpuid_eax(1) & 0xfffef) == 0x0f00;
}
static inline int is_cpu_pre_c0(void)
{
return (cpuid_eax(1) & 0xfffef) < 0x0f48;
}
static inline int is_cpu_c0(void)
{
return (cpuid_eax(1) & 0xfffef) == 0x0f48;
}
static inline int is_cpu_pre_b3(void)
{
return (cpuid_eax(1) & 0xfffef) < 0x0f41;
}
static inline int is_cpu_b3(void)
{
return (cpuid_eax(1) & 0xfffef) == 0x0f41;
}
//AMD_D0_SUPPORT
static inline int is_cpu_pre_d0(void)
{
return (cpuid_eax(1) & 0xfff0f) < 0x10f00;
}
static inline int is_cpu_d0(void)
{
return (cpuid_eax(1) & 0xfff0f) == 0x10f00;
}
//AMD_E0_SUPPORT
static inline int is_cpu_pre_e0(void)
{
return (cpuid_eax(1) & 0xfff0f) < 0x20f00;
}
static inline int is_cpu_e0(void)
{
return (cpuid_eax(1) & 0xfff00) == 0x20f00;
}
/* note: we'd like to have this sysinfo common to all K8, there's no need to
* have one different kind per different kind of k8 at this point.

1
mainboard/amd/serengeti/Makefile
View file

@ -26,6 +26,7 @@ STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
$(src)/northbridge/amd/k8/coherent_ht.c \
$(src)/northbridge/amd/k8/incoherent_ht.c \
$(src)/northbridge/amd/k8/libstage1.c \
$(src)/arch/x86/amd/model_fxx/stage1.c \
$(src)/lib/clog2.c
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \

61
northbridge/amd/k8/coherent_ht.c
View file

@ -286,10 +286,7 @@ u16 read_freq_cap(u32 dev, u8 pos)
freq_cap = pci_conf1_read_config16(dev, pos);
freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0())
#endif
#ifdef CONFIG_K8_HT_FREQ_1G_SUPPORT
{
return freq_cap;
}
@ -1595,9 +1592,6 @@ void coherent_ht_finalize(unsigned nodes)
{
unsigned node;
int dual_core = 0;
#if CONFIG_K8_REV_F_SUPPORT == 0
int rev_a0;
#endif
#if CONFIG_LOGICAL_CPUS==1
unsigned total_cpus;
@ -1617,9 +1611,6 @@ void coherent_ht_finalize(unsigned nodes)
*/
printk(BIOS_SPEW, "coherent_ht_finalize\r\n");
#if CONFIG_K8_REV_F_SUPPORT == 0
rev_a0 = is_cpu_rev_a0();
#endif
for (node = 0; node < nodes; node++) {
u32 dev;
u32 val;
@ -1648,13 +1639,6 @@ void coherent_ht_finalize(unsigned nodes)
(3 << HTTC_HI_PRI_BYP_CNT_SHIFT);
pci_conf1_write_config32(dev, HT_TRANSACTION_CONTROL, val);
#if CONFIG_K8_REV_F_SUPPORT == 0
if (rev_a0) {
pci_conf1_write_config32(dev, 0x94, 0);
pci_conf1_write_config32(dev, 0xb4, 0);
pci_conf1_write_config32(dev, 0xd4, 0);
}
#endif
}
printk(BIOS_SPEW, "done\r\n");
@ -1668,49 +1652,6 @@ int apply_cpu_errata_fixes(unsigned nodes)
u32 dev;
u32 cmd;
dev = NODE_MC(node);
#if CONFIG_K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Errata 66
* Limit the number of downstream posted requests to 1
*/
cmd = pci_conf1_read_config32(dev, 0x70);
if ((cmd & (3 << 0)) != 2) {
cmd &= ~(3<<0);
cmd |= (2<<0);
pci_conf1_write_config32(dev, 0x70, cmd );
needs_reset = 1;
}
cmd = pci_conf1_read_config32(dev, 0x7c);
if ((cmd & (3 << 4)) != 0) {
cmd &= ~(3<<4);
cmd |= (0<<4);
pci_conf1_write_config32(dev, 0x7c, cmd );
needs_reset = 1;
}
/* Clock Power/Timing Low */
cmd = pci_conf1_read_config32(dev, 0xd4);
if (cmd != 0x000D0001) {
cmd = 0x000D0001;
pci_conf1_write_config32(dev, 0xd4, cmd);
needs_reset = 1; /* Needed? */
}
}
else if (is_cpu_pre_d0()) { // d0 later don't need it
u32 cmd_ref;
/* Errata 98
* Set Clk Ramp Hystersis to 7
* Clock Power/Timing Low
*/
cmd_ref = 0x04e20707; /* Registered */
cmd = pci_conf1_read_config32(dev, 0xd4);
if(cmd != cmd_ref) {
pci_conf1_write_config32(dev, 0xd4, cmd_ref );
needs_reset = 1; /* Needed? */
}
}
#endif
}
return needs_reset;
}

7
northbridge/amd/k8/cpu.c
View file

@ -129,6 +129,7 @@ static unsigned int cpu_bus_scan(struct device * dev, unsigned int max)
}
#warning clean this mess up
e0_later_single_core = 0;
if (dev && dev->enabled) {
j = pci_read_config32(dev, 0xe8);
@ -141,11 +142,7 @@ static unsigned int cpu_bus_scan(struct device * dev, unsigned int max)
// That is the typical case
if(j == 0 ){
#ifndef CONFIG_K8_REV_F_SUPPORT
e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else
e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
#endif
e0_later_single_core = 1; // we are all f0 or later now. is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
} else {
e0_later_single_core = 0;
}

10
northbridge/amd/k8/domain.c
View file

@ -262,9 +262,6 @@ static void k8_pci_domain_set_resources(struct device * dev)
* if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
* otherwise We reset the hole to the mmio_basek
*/
#ifndef CONFIG_K8_REV_F_SUPPORT
if (!is_cpu_pre_e0()) {
#endif
mem_hole = get_hw_mem_hole_info();
@ -303,10 +300,6 @@ static void k8_pci_domain_set_resources(struct device * dev)
#endif
}
#ifndef CONFIG_K8_REV_F_SUPPORT
} // is_cpu_pre_e0
#endif
#endif
idx = 0x10;
@ -346,9 +339,6 @@ static void k8_pci_domain_set_resources(struct device * dev)
}
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
if(reset_memhole)
#ifndef CONFIG_K8_REV_F_SUPPORT
if(!is_cpu_pre_e0() )
#endif
sizek += hoist_memory(mmio_basek,i);
#endif

8
northbridge/amd/k8/incoherent_ht.c
View file

@ -158,13 +158,7 @@ static u16 ht_read_freq_cap(u32 bdf, u8 pos)
/* AMD K8 Unsupported 1Ghz? */
if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
#if K8_HT_FREQ_1G_SUPPORT == 1
#if K8_REV_F_SUPPORT == 0
if (is_cpu_pre_e0()) { // only E0 later support 1GHz
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
}
#endif
#else
#ifndef K8_HT_FREQ_1G_SUPPORT
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
#endif
}

1
northbridge/amd/k8/raminit.c
View file

@ -24,6 +24,7 @@
2004.12 yhlu add D0 support
2005.02 yhlu add E0 memory hole support
*/
#warning use raminit_f.c not this one.
/* not yet
#if K8_REV_F_SUPPORT == 1
#include "raminit_f.c"