The FSP Temp RAM init will fail if the mircocode values are set
to 0. A valid microcode update needs to be included and its size
and offset need to be set in the config.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iac912e7350662a9e56aae6eb80b70fca5c032fd3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6b8570d864
Original-Change-Id: I26d05bd7b37c8d91bf34f399c7c4189f9d3dd34a
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19936
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531690
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Adding code to setup the spd information from sodimm.
Adapted from intel/kblrvp.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iffd47fc71def3533fb7545abe753fd09df77e184
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0e977fca9c
Original-Change-Id: I0403f999dac1bdef0e9e1abe7c9c62407e223bb1
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19935
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531689
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The GPIO configuration matches the one from the original BIOS.
Some configs don't make much sense, but I kept it as is so it
would match (such as a NC pin with TX set to 1, or RXINV enabled).
Remove unnecessary early GPIO config.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id7d3d5537260431af116b017ad5860d95adf781c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 34a30a648f
Original-Change-Id: Iaec8630cef9a523fb2e2503143aa4aa72fbedc1f
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19934
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531688
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Like other devices using ENE embedded controllers, the librem13v2
requires this config option for the PS2 keyboard and mouse
(trackpad) to function properly.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6a4309052ac05fafe88e7ec61e52dcdb5a320559
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2766ebf585
Original-Change-Id: Ifba13b93a1fe2e76b2790d1c273fd9e2b5368ab0
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19933
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531687
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add the initial directory for the port of the Librem 13 v2.
The base implementation was copied from the google/chell directory
and the chell references were replaced. spd directory was removed
since the RAM is not soldered on the MB. The Kconfig, board_info.txt
and devicetree.cb files were modified to match the Librem 13 v2
hardware information. The romstage.c, mainboard.c, Makefile.in and
dsdt.asl were modified to remove chromeos specific code. The boardid.c,
chromeos.c, chromeos.fmd, cmos.layout, ec.c, ec.h and smihandler.c
files were removed from the tree, and the acpi directory was replaced
with the acpi directory from the purism/librem13 board.
These changes allow us to remove the references to chromeos specific
code and allow coreboot to compile when the librem13v2 board is selected.
BUG=none
BRANCH=none
TEST=none
Change-Id: I44e7be967bf4e72e086aa26d332ac6dd16ae0608
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 047475cbd7
Original-Change-Id: I24263fde18fcea70163dbdc59df6ea1d98c97af8
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19932
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531686
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The FADT revision was set to 5, but we do not implement the
ACPI v5.0 specification, which prevents Windows from booting.
Setting it to v3 (matching most other boards) fixes the issue
and Windows now boots normally.
Bug found by Matt DeVillier, fix tested by Youness Alaoui on
Librem 13 v1 hardware.
Please also see commits 00d250e228 (intel/skylake: Switch FADT
to ACPI version 3.0) [1] and 27e6042bb7 (intel/apollolake:
Switch FADT to ACPI version 3.0) [2].
[1] https://review.coreboot.org/19453
[2] https://review.coreboot.org/19146
BUG=none
BRANCH=none
TEST=none
Change-Id: I24a5d1d75ef0fca5b273d8d32d20812089850812
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ab5b4c19c3
Original-Change-Id: Ide97cbf64f7b05018433436431ab4723b217fe22
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19985
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531685
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The Role-Based Error Reporting is not a configurable field,
it's a read only field in the Device Capability register.
This code was old and comes from commit f6eb88ad but evidently
is not useful in any way. The PCIe Specification [1] states
that it's read-only and must always be set to 1.
I have also done tests on purism/librem13 hardware, trying to
change that value, without any success.
[1]: PCI Express Base Specification Revision 3.0
Page 612
BUG=none
BRANCH=none
TEST=none
Change-Id: Id4dff17957fbd6e1f54ab0917d4f9c7b557149d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2f48b7b1e9
Original-Change-Id: I729617a5c6f4f52dfc4c422df78379b309066399
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19901
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531684
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The ASPM options (L1 substates, CLKREQ support, Common Clock and ASPM)
are hardcoded for broadwell chips, but some boards may not support
these ASPM options even if the SoC does support it (non-wired CLKREQ
pin for example).
This is required to disable L1 substates on the Purism/Librem 13 which
seems to have issues with NVMe drives falling into L1.2 state and not
being able to exit that state.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifde46a1db3702a6e1ad49cf3cb03a61d6ffe82d4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b191c9f0ab
Original-Change-Id: I2c7173af1d482cccdc784e3fa44ecbb5d38ddc34
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19899
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531203
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The PCIe specification[1] describes a race condition that
can occur when using the Retrain Link bit in the Link
Control Register.
The race condition is avoided by checking the retrain link
bit in the link status register and waiting until it is
set to 0, before initiating a new link retraining.
[1] PCI Express Base Specification Revision 3.0
Page 633
BUG=none
BRANCH=none
TEST=none
Change-Id: I9ebdb696f63706590bf864f4b3e11304a1f7a1b4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bb5fb64e11
Original-Change-Id: I9d5840fb9a6e63838b5a4084d3bbe483f1d870ed
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19556
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531202
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
A simple rename of the directory and the config values
and string in Kconfig/Kconfig.name/board_info.txt
It will be less confusing for users since the first models
are referred to as 'v1' everywhere now.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7a5bc84a564a6e75f0be9b34957ec09031fd368c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3c0d7d21ef
Original-Change-Id: I23fa977717230c2001868741bb684e9633a2c0bb
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19931
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/531201
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Adapted from Chromium commit 8fbe1e7 for soc/braswell
(also review.coreboot.org/#/c/20060/); same issue affects
baytrail as well.
This patch recollects TOLM accessing; as Aaron recalled some
core_msr_script turns off access to TOLM register, he suggests
to store tolm to avoid getting back a zero while setting acpi
nvs space.
BUG=none
BRANCH=none
TEST=none
Change-Id: I87cc97e3d8270801b6924b310919ad7293f17626
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f05d2e17b0
Original-Change-Id: Ib26d4fe229b3f7d8ee664f5d89774d1f4a997f51
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20081
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531200
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Each I2C controller should have a unique pair of DMA request lines,
and DMA channels should be assigned incrementally, rolling over as
necessary.
Source: Intel Baytrail/ValleyView UEFI reference code
BUG=none
BRANCH=none
TEST=none
Change-Id: I69c3bd55f6340770402a67af2601e5df965b2b60
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 930577ac7b
Original-Change-Id: Icc9b27aaa14583d11d325e43d9165ddda72ca865
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20080
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531199
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Each I2C controller should have a unique pair of DMA request lines,
and DMA channels should be assigned incrementally, rolling over as
necessary.
Source: Intel Braswell UEFI reference code
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic4cffd5dce2387288f5b8559f497230b22ddce90
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f6cfa71217
Original-Change-Id: I1d97b5a07bf732c27caf57904c138b120b93ca81
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20079
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531198
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Use common init_igd_opregion method.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7b93ffe4853c129e3acc0126fb85fe8519d058ab
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9095e2f50e
Original-Change-Id: Ie70a49fd532b7ad7679dc558cc4a019a273a0602
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19906
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531197
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Copy Haswell's init_igd_opregion to common folder.
Remove platform specific code.
Will replace all Intel NB implementations.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3886dfb0c4a3c98cfb6c0c68a14852d88f0f5a8d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 96c3ef81fc
Original-Change-Id: I14dfb5986df264ffd71183a159f98b79e8e3230e
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19905
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531196
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Type 0x10 is mini RDIMM according to JEDEC DDR2 SPD
specifications.
BUG=none
BRANCH=none
TEST=none
Change-Id: I35c9634f36868caf03438e688c1ec5ab484c2449
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 87f7588c50
Original-Change-Id: I6d35bd74961326ebd9225f044313b107aca24bda
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20058
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/531195
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Commit 7c634ae8 (msrtool: added support for Intel CPUs) adds `no-pic` to
the compiler flags.
GCC 7.0.1 20170316 fails to built with the error below.
```
/usr/bin/ld: msrtool.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: msrutils.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: sys.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: linux.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: freebsd.o: relocation R_X86_64_32S against `.data' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: final link failed: Nonrepresentable section on output
```
Removing the flag causes the build to succeed with GCC 7, 6.3, and clang
4.0.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iba6a3ce9e098c60cf6ec6a6cd6d649df15486b91
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 459d2198eb
Original-Change-Id: I3d7aed27ce7f84aa27305c68e2d5f14607c58ec8
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18907
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Original-Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531194
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
For an unknown reason, the I2C ACPI devices were placed
under \SB intead of \SB.PCI0, as with all other non-Atom
based Intel platforms. While Linux is tolerant of this,
Windows is not. Correct by moving I2C ACPI devices where
they belong.
Also, adjust I2C devices at board level for intel/strago
and google/cyan as to not break compilation.
BUG=none
BRANCH=none
TEST=none
Change-Id: I39d845ba3b6d07d8bb5f63f663316750f03f20a6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6a67ffb6ea
Original-Change-Id: Iaf8211bd86d6261ee8c4d9c4262338f7fe19ef43
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20055
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531193
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibca733ea7c557899ff2f8d86362cccd7a41bbcca
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 397c7b3411
Original-Change-Id: Ie0b64eadc634049f6b65cf555407337fb7c4363c
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19976
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531192
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9f566b4c7117981e58709d3b8b52b410a5e3bbaf
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dc1b78130a
Original-Change-Id: I14ba3cea821e103208426e9fcaa0833d84157ff8
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19975
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531191
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Switch from lapic to tsc.
Allows timestamps to be used in coreboot, as there's a reference
clock available to calculate correct time units.
Clean Kconfig, remove duplicated lapic code and include tsc dir for
LGA1155 boards.
Tested on Lenovo T430.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4c179884707380e1417a251db8f70d0a915572af
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b9959e279c
Original-Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20044
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531190
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I0b3a475c1c875e51929e981d7a809f5e40b00e43
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 21e7424fc9
Original-Change-Id: I751e887bd90a258a69d13ea4ee9a409c8c86a3c3
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19591
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531189
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Update user facing camera i2c address to 0x36.
BUG=None
TEST=Build & boot on soraka. Make sure user facing camera is detected.
Change-Id: Id441041035e8a2962c859cac93d02858fc84d625
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5e10422df2
Original-Change-Id: I4645ae5734faef4b6a821c04ab817a7b99da6e4b
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20023
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/531188
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The RTC RX6110SA has several configuration options which might be
interesting to set. To make this setup independent of the driver itself
but let it still be configurable on mainboard level, add more
configuration options to the chip driver.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2050f013241e3ff6021ec1eb9aabf91f6d725229
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0dc405de98
Original-Change-Id: I7f8b2aa7cd001a887f271be36f655e10e60e778b
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/20084
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/531187
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
GCC version 7 is being a bit picky about pointer and integer comparison
by default, which triggers a crossgcc build error.
This backports a patch from upstream GCC to fix the issue.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie3424a428121ac8dead85707e691bd4d60e69183
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 37afb270b4
Original-Change-Id: I8b1e806c10604c0df080ac5edc667bf1141e2c17
Original-Signed-off-by: Paul Kocialkowki <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/20103
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531186
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the
reference clock can be 100Mhz.
Decode the register and use the reference clock to calculate
the selected DDR frequency.
Tested on Lenovo T430.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia5f46992e4d536a21922721eb97061a78e067e74
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6ab7e5e090
Original-Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19995
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/528271
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add additional ACPI opcodes, that are going to be used in the
following commits.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icc2d79902965feca18c5c502dffcd189329b4c44
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a038835716
Original-Change-Id: I20c3aa5a1412e5ef68831027137e9ed9e26ddbc9
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20087
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/528270
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fix regression introduced by commit 5c026445
(drivers/intel/wifi: Add support for generating SSDT table)
In case the regular PCI path is taken, there're no chip_ops and the code
will segfault. The bug was covered by other bugs that caused this code
to never execute.
Add NULL pointer checks and only fill in device name if one is provided.
Tested on Lenovo T430 and wifi card 8086:0085.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ieb95c7f281d8f69ecf3cc2e0e176a24923891a2f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6086b4ee38
Original-Change-Id: I84e804f033bcd3af1a7f76670275fdf5159d381f
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20082
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/528269
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Because the help block uses significant whitespace to determine whether
or not text is inside the help block, a mixture of spaces and tabs
confuses the parser.
If there's an unrecognized line, and the previous line was inside a help
block, it's likely that this line is too.
Additionally, this was found with a line that started ' configuration',
and threw a perl warning about an uninitialized value because the parser
thought this was the start of a new config line, but couldn't find the
symbol. Now we make sure that config statements have whitespace after
the 'config' statement.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5d564165c3842bb64f16db1ee85d24d4bd2dfc52
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 811d93af39
Original-Change-Id: I46375738a18903b266ea9fff3102a1a91235e609
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19155
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528268
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add a target to show what files are used in the build. This was already
being generated for other targets, but there was no target to just
generate and view the list.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia8083371f4337a905b94e1325bef8056d2d37a07
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a18353d7b7
Original-Change-Id: I6998296bb135d8b7170cacae2be902ef9dac7b54
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/20049
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528267
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
- Turn the check for help text with no indentation from a warning to
an error.
- Show an error if the help text is at the same indentation level as
the 'help' keyword.
BUG=none
BRANCH=none
TEST=none
Change-Id: I743c991b27887e6e02b45fe1ec42a06005a4dc07
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 8849f3be4a
Original-Change-Id: Ibf868c83e2a128ceb6c4d3da7f2cf7dc237054e6
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19851
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/528266
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove spi_init definitions which:
1. Do nothing
2. Set static global variables to 0
BUG=none
BRANCH=none
TEST=none
Change-Id: I471dc31bf496936968c3a4a55f7ecac517752e5d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2dafd89769
Original-Change-Id: If4c0cdbe2271fc7561becd87ad3b96bd45e77430
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20039
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/528265
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add support for ELAN 5515 device.
BUG=b:62331218
Change-Id: I1be493f7fbce0a31fefdc589c063d1561a384c5e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5677e7da4b
Original-Change-Id: Id91a41743330c9e356293cfda7b2e3743dcd480c
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20040
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528264
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
These Kconfig files had help text that was not indented further than
the 'help' keyword.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia652cab86f965ba95ad2105f37493c7a53c52f97
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f482396625
Original-Change-Id: Ia9fdb22c0f5f0cec0c9d08aa6603b4ce8d60d9a3
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19850
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528263
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fix up commit 26174c97 (abuild: Build saved config files)
unintentionally adding a space before a tabulator.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id11e2f532857cfb0e6c47fe57a3b1ed1e3d17ce6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d2bbaffe40
Original-Change-Id: Ic51dee6ed9d640335c2bde5bd5dfad3691c505e0
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/17778
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528262
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch fixes ACPI debug print issue reported internally
while using APRT asl method. Potentially some junk characters
gets added into final print buffer due to LPSS MMIO register
space is 32 bit width and ADBG is one byte at a time.
TEST=Built and boo eve to ensure to be able to get ASL console
log without any corruption.
Change-Id: Ia5a03c7874d5b50f6259a95c8e8896d0e616cfd7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f0c7be4e63
Original-Change-Id: I0b6af789c0ffc79f7fee4652b4aa6a125b182296
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20009
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/528261
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This symbol can be selected (e.g. in site-local/) to disable the user
friendly but annoying default payload choice.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7b2d825a5af5b22f5c1182933ef76049344a85ce
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9121a364a6
Original-Change-Id: I2f72d4efc0a428dce377c3d003b2c00a6c8d4c08
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19808
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528260
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
BUG=none
BRANCH=none
TEST=none
Change-Id: I280a7abeada01b4d158b2d65c3b59f1b98b81ad9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e18e6427d0
Original-Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/20029
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528259
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9aeccd7b0dcf3ea7b8801c76251b7409a79b99d4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e81ce0483d
Original-Change-Id: I2ec18ca55e0ea672343a951ab81a24a5630f45fd
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/20028
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/528258
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
<https://coreboot.org> is redirected to <https://www.coreboot.org>.
```
$ curl -I https://coreboot.org
HTTP/1.1 301 Moved Permanently
Server: nginx/1.8.1
Date: Mon, 05 Jun 2017 10:41:33 GMT
Content-Type: text/html
Content-Length: 184
Connection: keep-alive
Location: https://www.coreboot.org/
```
So use the command below to use the final location to save a redirect.
```
$ git grep -l https://coreboot.org \
| xargs sed -i 's,https://coreboot.org,https://www.coreboot.org,g'
```
BUG=none
BRANCH=none
TEST=none
Change-Id: I4978d8311a07870aee41103912c218ced4569611
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 59e2113670
Original-Change-Id: I4176c20ef31399f0063b41e3a0029cca0c1b0ff3
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/20035
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528257
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.
Run the command below to replace all occurences.
```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```
BUG=none
BRANCH=none
TEST=none
Change-Id: I881e55138a6114c67585ce37d4d719fe2626b83a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a8843dee58
Original-Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/20034
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528256
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Wrapping the long line tries to address a warning by `checkpatch.pl`,
but the line is still over 80 characters long.
BUG=none
BRANCH=none
TEST=none
Change-Id: If63c7ff3fb041b070dc815ffe05592edbb03dbec
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 619e83045a
Original-Change-Id: Ib75d4da1880624eb83f7a419cb6762f1c4c2a7b2
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/20033
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528255
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The comma-separated PCI vendor and device ID is used to associate the
VGA BIOS to the video device by using it as the file name of the VGA
Option ROM.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ideb80c381f491925dba2931448fe125a3f54e8f7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e213bf3767
Original-Change-Id: I755554eeb9a560d034d6e8fe49de619d800ea045
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18741
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528254
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
When using the regular `if` construct, the compiler will check the
guarded code independently from the condition.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib96966f0b9a22f751c0e359ceaa2c4503cc4d914
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: afbc2c9c0c
Original-Change-Id: I988fa9379e8c748013a67ef29fa908b4d9a970ad
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18794
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528253
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Device ID is read from HP Elitebook 2760p.
Based on:
- superio/smsc/kbc1100 (LDNs, keyboard, EC)
- DSDT from OEM firmware (COM1 and mailbox)
- Datasheet "KBC1122 Priliminary DS Rev. 0.8"
BUG=none
BRANCH=none
TEST=none
Change-Id: I336a8de9fc227086e8f6e41296360ef84511e0e8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7f46fff24c
Original-Change-Id: Id172ae42411a6d42a4ae7c7f30f96aeda3e6c384
Original-Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18480
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/528252
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove PCI IDs inclusion from soc header rather referring those
from device/pci_ids.h.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie89777bc73c7061676e740f10ada60e1391b312d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c2165671b0
Original-Change-Id: I490da3e336fb6f8194d5fba800132f550ed5ab37
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20015
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/528191
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
GCC7 has a new feature called -Wimplicit-fallthrough enabled by
default which checks for fallthrough in switch statements which is a
common error. When a fallthrough is actually intended a comment saying
so will satisfy GCC.
Fixes cbfstool not building with GCC7.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ieb0affec0b5ea2c651469f92d5c15bf57cdc6cf8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 54fd92bc34
Original-Change-Id: I83252fc96be7ce0971d4251b0fc88fbbd7440e71
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20036
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/528190
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
coreboot doesn't support CMOS options that are not byte aligned but
span multiple bytes. So treat them as error.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6612546b44a3d50158b674106fb62e3948561b3e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3af6985050
Original-Change-Id: I2bcff62f153932e9c6646b4ce08e8da1c1532947
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/18246
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/528189
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Changes the offsets of some options so that options that span multiple
bytes are byte aligned.
To make the cmos.layout file more consistent some things where moved
around in the cmos.layout of thinkpads X200 and T400.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8736136043c526817fc12f52d37a5a1db4fb95b9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 00b9f4c4b1
Original-Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18321
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/528188
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I6ec991d905e16f79eaa162f07c79c1c0f8b85a61
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b40e5c72b7
Original-Change-Id: Ieeb53a1694193cd19b5e9aa5bee25e36a60e56bd
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19054
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528187
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
